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Predictable synchronous components for high-performance embedded systems

Predictable synchronous components for high-performance embedded systems

Objective

The TOK-IAP PSYCHES project will allow to build knowledge for the development of low cost, high performance highly parallel architecture and methodology for the high demanding video consumer appliances, closing the gap between the performance density of dedicated hardware and the flexibility of programmable approach. The research project, build from the exchange of knowledge between Philips, INRIA and UPC, relies on the following key research aspects:
- A sound, theoretical model allowing to build systems and software "correct by construction".
- A compiler technology allowing extracting wide parallelism from domain specific applications. We believe that in the domain of embedded video processing this can be achieved with state-of the art technique developed in INRIA and UPC.
- An efficient communication infrastructure or memory hierarchy, allowing to feed a high number of compute units simultaneously.
- An optimised, but yet open to a wide variety of applications in the video processing domain.
We advocate that, provided we strike the right balance between the architecture, compiler and user effort, it is possible to unveil multi-grain parallelism and to take advantage of it without excessively complex architectures or compilers. As seen, the multidisciplinary approach is mandatory to the success of the project, and the various cultures of the participants - industrial (Philips), theory and compilation (INRIA), architectures (UPC)- is the strong point for this Transfer Of Knowledge.
The true complementarities of Philips, INRIA and UPC will be necessary to successfully follow this approach that will pave the way to new research projects that will bring a new family of systems that could outperform the US dominated microprocessors for high performance embedded consumer applications, giving to Europe a leading edge in this market.

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Coordinator

NXP SEMICONDUCTORS NETHERLANDS BV

Address

High Tech Campus 60
Eindhoven

Netherlands

Administrative Contact

Peter ZEGERS

Participants (3)

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INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET AUTOMATIQUE, UNIT??????A? DE RECHERCHE FUTURS

France

UNIVERSITAT POLITECNICA DE CATALUNYA

Spain

PHILIPS ELECTRONICS NEDERLAND B.V.

Netherlands

Project information

Grant agreement ID: 30072

  • Start date

    1 March 2006

  • End date

    28 February 2009

Funded under:

FP6-MOBILITY

Coordinated by:

NXP SEMICONDUCTORS NETHERLANDS BV

Netherlands