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Extended Large (3D) Integration TEchnology

Project information

Grant agreement ID: 215030

Status

Closed project

  • Start date

    1 November 2007

  • End date

    31 August 2011

Funded under:

FP7-ICT

  • Overall budget:

    € 5 628 834

  • EU contribution

    € 3 600 000

Coordinated by:

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

France

Project description

Next-Generation Nanoelectronics Components and Electronics Integration 3-D integration in high performance digital systems For developing complex next-generation chips which include a combination of disparate technologies, the circuit integration exclusively in two dimensions has proved to be a seriously limiting factor. Utilising the third dimension for integration of complex chips is a promising technique for removing the bottlenecks in two-dimensional (2-D) integration. Advantages of third-dimension (3-D) integration are in first order form factor and power dissipation.The project ELITE aims at miniaturization and density increase beyond conventional limits by means of exhaustive die stacking. It takes as development vehicle an advanced solid state drive which will widely substitute traditional hard disk drives for purpose of mobile and hand-held applications and which is considered as the enabler of the increasingly developing era of mobile data. The system architecture includes a large amount of non-volatile flash memory, one or more microcontrollers and external analog high-speed interface.One of the main topics of ELITE is the development of a technology for vertical die stacking and for vertical interconnect. Starting from the expertise and experience of the consortium new technology modifications or alternative technologies are investigated. Also assembly technology is investigated considering possible later usage in mass-production with its specific requirements on manufacturability and cost. Conceptual and physical simulations are deployed for planning and ensuring the system architecture and specifying a demonstrator to prove the feasibility of the concept. Firmware inside the chip is used to optimize performance by means of parallel tasks, guarantee highly reliable data access as well as controlling power dissipation.As a final step, generalization of the results which are reached with the solid-state drive vehicle can be generalized in order to be re-used for applications from different technical domains and markets.

Coordinator

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Address

Rue Leblanc 25
75015 Paris 15

France

Activity type

Research Organisations

EU Contribution

€ 1 369 639

Administrative Contact

Marie-Laure Page (Ms.)

Participants (5)

QIMONDA FLASH GMBH

Germany

EU Contribution

€ 480 958

HYPERSTONE GMBH

Germany

EU Contribution

€ 514 731

Numonyx Italy Srl

Italy

EU Contribution

€ 389 568

KUNGLIGA TEKNISKA HOEGSKOLAN

Sweden

EU Contribution

€ 430 937

UNIVERSITY OF LANCASTER

United Kingdom

EU Contribution

€ 414 167

Project information

Grant agreement ID: 215030

Status

Closed project

  • Start date

    1 November 2007

  • End date

    31 August 2011

Funded under:

FP7-ICT

  • Overall budget:

    € 5 628 834

  • EU contribution

    € 3 600 000

Coordinated by:

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

France