Obiettivo The overall objective of this programme was to develop a specific submicron bipolar technology suitable for manufacturing very high performance integrated circuits, such as high-speed circuits for Electronic Data Processing (EDP) and Digital Signal Processing (DSP). At the start of the programme the majority of advanced bipolar processes used 1-1.5 micron feature sizes exhibiting gate delays of 200 ps and an integration level of less than 5000 gates. The target at the end of the project was to develop a submicron process with <100 ps gate delays and integration levels of 20 000 gates. Such a large change in the state of the art required a two-stage development programme with two separate processes and demonstrators, produced in years 3 and 5 of the programme. The overall objective of this programme was to develop a specific submicron bipolar technology suitable for manufacturing very high performance integrated circuits.During the execution of this programme the following processes were developed:trench etching;trench etchback;hyper shallow emitter base by implantation through oxide or by direct BF2 implantation;rapid thermal annealing for the emitter base;double polysilicon contact structures;polycide interconnect;new intrinsic gettering techniques;improved stepper lithography.These techniques have been assembled into a single process.2 supplementary research topics were also pursued, SELOX technology and new polyimides.2 demonstrators were produced using a common gate array concept. Both demonstrators used a similar 3 transistor cell gate array with resistors trimmed using the silicide mask. The demonstrators had a similar area, but the submicron demonstrator had approximately twice as many transistors.During the execution of this programme the following processes were developed: trench etching; trench etchback; hyper shallow emitter base by implantation through oxide or by direct BF2 implantation; rapid thermal annealing for the emitter base; double polysilicon contact structures; polycide interconnect; new intrinsic gettering techniques; improved stepper lithography. These techniques have been assembled into a single process as outlined below: 1-micron processSubmicron process Process featuresTrench isolationTrench isolationPolysilicon emitterPolysilicon emitterThermal drive-inRTA drive-inSingle poly contactsDouble poly contacts Unit gain frequency (GHz)9>15 Gate delay100 ps50 ps Power delay product130 fJ60 fJ Metal pitch6 microns4 microns Demonstrator17K transistors45K transistors Two supplementary research topics were also pursued, SELOX technology and new polyimides. In the case of SELOX technology, a novel sidewall contacted structure was developed by the Technical University of Berlin. Basic transistors were demonstrated and a full investigation of the concept was undertaken. Thomson LCR, Rhone Poulenc and Cemota worked on new polyimides. The stability of these new materials was investigated and research was performed on low dielectric constant materials. The industrial partners were also involved in evaluation of these new materials. During the five-year project, two demonstrators were produced using a common gate array concept. Both demonstrators used a similar three-transistor cell gate array with resistors trimmed using the silicide mask. The submicron demonstrator used a 66% scaled layout. The demonstrators had a similar area of 10 x 8 mm, but the submicron demonstrator had approximately twice as many transistors. The customisation for the one-micron demonstrator consisted of a 4x512 stage shift register that operated at 950MHz. The design was performed by all the industrial partners. The submicron demonstrator underwent two customisations. The first, designed by the Technical University of Berlin, consisted of a four-tap digital filter for HDTV applications. The circuit is essentially a digital transversal filter consisting of a 12 bit shift register, four 12 x 16 multipliers, summation elements, and control logic. A second customisation is a 10 000-gate array capable of clock frequencies of up to 2.5 GHz. This is a programmable delay line that includes 1036 d-type flip-flops operating at a clock rate of 1 GHz. Exploitation At the end of the project a number of high-performance parts were in the pre-production stages. They included dividers, PLL synthesisers, direct frequency synthesisers, and analogue/digital and digital/analogue converters. In addition, this technology wasused in various RACE programme projects. The enhancement and exploitation of this technology is taking place under project 2016 (BASE-TIP). Campo scientifico engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringsignal processingnatural sciencescomputer and information sciencesdata sciencedata processing Programma(i) FP1-ESPRIT 1 - European programme (EEC) for research and development in information technologies (ESPRIT), 1984-1988 Argomento(i) Data not available Invito a presentare proposte Data not available Meccanismo di finanziamento Data not available Coordinatore GEC Plessey Semiconductors plc Contributo UE Nessun dato Indirizzo Caswell NN12 8EQ Towcester Regno Unito Mostra sulla mappa Costo totale Nessun dato Partecipanti (5) Classifica in ordine alfabetico Classifica per Contributo UE Espandi tutto Riduci tutto CEMOTA Francia Contributo UE Nessun dato Indirizzo 69390 VERNAISON Mostra sulla mappa Costo totale Nessun dato Technische Universität Berlin Germania Contributo UE Nessun dato Indirizzo Jebensstraße 1 10623 Berlin Mostra sulla mappa Costo totale Nessun dato Telefunken Microelectronic GmbH Germania Contributo UE Nessun dato Indirizzo Theresienstraße 2 74072 Heilbronn Mostra sulla mappa Costo totale Nessun dato Thomson CSF Francia Contributo UE Nessun dato Indirizzo Domaine de Corbeville 91404 Orsay Mostra sulla mappa Costo totale Nessun dato Thomson CSF Francia Contributo UE Nessun dato Indirizzo 38 rue Vauthier 92100 Boulogne-Billancourt Mostra sulla mappa Costo totale Nessun dato
