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Architecture Paradigms and Programming Languages for Efficient programming of multiple CORES

Architecture Paradigms and Programming Languages for Efficient programming of multiple CORES

Objective

Apple-CORE will develop compilers, operating systems and execution platforms to support and evaluate a novel architecture paradigm that can exploit many-core chips to the end of silicon. It adopts a systematic model of concurrency implemented as instructions in the processors' ISA (developed in the EU FP6 AETHER project). This has enormous potential but is disruptive, as this paradigm shift requires a new infrastructure of tools. The benefits are large, however, as compilers need only capture concurrency in a virtual way rather than capturing, mapping and scheduling it. This separates the concerns of programming and concurrency engineering and opens the door for successful parallelising compilers. Mapping and scheduling is performed dynamically by implementations of the concurrency control instructions in the processors ISA. Another advantage of this approach is its binary compatibility. This means backward compatibility over a base ISA and forward compatibility as compiled code is executable on an arbitrary numbers of processors. Ths compatibility also enables dynamic resource mapping to binary programs from a pool of processors. Particular benefits can be expected for data-parallel and functional programming languages as they expose concurrency in a way that can easily be captured by a compiler. As well as computational benefit the ISA supports the management of partial failure, which provides support for reliable systems. Finally, this approach exposes information about the work to be executed on each processor and how much can be executed at any given time. This information can provide powerful mechanisms for the management of power by load balancing processors based on clock/ frequency scaling. The objective of developing this infrastructure is to evaluate the model and provide opportunities to exploit the results of this research in a variety of markets, including embedded and commodity processors, and also high-performance applications.
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Coordinator

UNIVERSITEIT VAN AMSTERDAM

Address

Spui 21
1012wx Amsterdam

Netherlands

Activity type

Higher or Secondary Education Establishments

EU Contribution

€ 905 572

Administrative Contact

Christopher Roger Jesshope (Prof.)

Participants (5)

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USTAV TEORIE INFORMACE A AUTOMATIZACE AV CR VVI

Czechia

EU Contribution

€ 328 731

PANEPISTIMIO IOANNINON

Greece

EU Contribution

€ 115 470

ACE ASSOCIATED COMPILER EXPERTS B.V.

Netherlands

EU Contribution

€ 156 371

COBHAM GAISLER AB

Sweden

EU Contribution

€ 127 430

THE UNIVERSITY OF HERTFORDSHIRE HIGHER EDUCATION CORPORATION

United Kingdom

EU Contribution

€ 466 420

Project information

Grant agreement ID: 215216

Status

Closed project

  • Start date

    1 November 2007

  • End date

    30 April 2011

Funded under:

FP7-ICT

  • Overall budget:

    € 2 751 973

  • EU contribution

    € 2 099 994

Coordinated by:

UNIVERSITEIT VAN AMSTERDAM

Netherlands