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Mapping Optimisation for Scalable multi-core ARchiTecture

Mapping Optimisation for Scalable multi-core ARchiTecture

Objective

Key Innovation

The widening gap between performance requirements of applications and their related power consumption and what is afforded by technology scaling and architectural techniques clearly focuses the multiprocessor  architectures as the today and future solution for computing and embedded systems. The present day wireless,  multimedia and networking standards requires already several processors in a chip. The challenge going forward is to be able to sustain several applications such agile spectrum radios, future internet connectivity, 3D media and trusted computing, … that are at least several order of magnitude more demanding than the existing standards.
Also memory impacts the cost, power and performance of heterogeneous multi-processor architectures. The need for large amount of storage and a high bandwidth access to it comes from two ends. The primary need comes from the applications becoming more multi-functions and data intensive (high resolution, higher bandwidth communication etc.). The secondary need comes from the requirement to hide the latency of accessing slower off chip memory.
As such MOSART addresses novel architectures for multi-core computing systems in embedded systems, the project defines and develops the Software/Hardware design environment encompassing a flexible, modular, multi-core, on-chip platform, and associated exploration methods and tools, to allow the scaling and optimisation of various applications in multimedia and wireless communication.

Technical approach

MOSART addresses two main challenges of the prevailing multiprocessing architectures: the global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; and the difficulties in programming heterogeneous, Multi-core platforms, in particular, in many cores and in dynamically managing data structures in distributed memory.
MOSART aims to overcome these challenges through a multi-core architecture with distributed memory organization, a network-on-chip (NoC) communication backbone, and configurable processing cores that are scaled, optimized, and customized to achieve diverse energy, performance, cost, and size requirements of different classes of applications.
MOSART achieves this by providing platform support for managing abstract data structures, including middleware services and a runtime data manager for NoC-based communication infrastructure; and developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.

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Coordinator

THALES SIX GTS FRANCE SAS

Address

Avenue Des Louvresses 4
92230 Gennevilliers

France

Activity type

Other

EU Contribution

€ 699 922

Administrative Contact

Gwenael GUILMIN (Dr.)

Participants (9)

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INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM

Belgium

EU Contribution

€ 372 325

SNPS BELGIUM NV

Belgium

EU Contribution

€ 91 790

LT DESIGN SOFTWARE GMBH

Germany

EU Contribution

€ 280 659

TEKNOLOGIAN TUTKIMUSKESKUS VTT

Finland

EU Contribution

€ 362 547

ARTERIS SA

France

EU Contribution

€ 184 555

DIMOKRITIO PANEPISTIMIO THRAKIS

Greece

INSTITUTE OF COMMUNICATION AND COMPUTER SYSTEMS

Greece

EU Contribution

€ 388 448

INTRACOM SA TELECOM SOLUTIONS

Greece

EU Contribution

€ 269 750

KUNGLIGA TEKNISKA HOEGSKOLAN

Sweden

EU Contribution

€ 450 004

Project information

Grant agreement ID: 215244

Status

Closed project

  • Start date

    1 January 2008

  • End date

    31 December 2010

Funded under:

FP7-ICT

  • Overall budget:

    € 4 462 899

  • EU contribution

    € 3 100 000

Coordinated by:

THALES SIX GTS FRANCE SAS

France