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Mapping Optimisation for Scalable multi-core ARchiTecture

Descrizione del progetto


Computing Systems

Key Innovation

The widening gap between performance requirements of applications and their related power consumption and what is afforded by technology scaling and architectural techniques clearly focuses the multiprocessor  architectures as the today and future solution for computing and embedded systems. The present day wireless,  multimedia and networking standards requires already several processors in a chip. The challenge going forward is to be able to sustain several applications such agile spectrum radios, future internet connectivity, 3D media and trusted computing, … that are at least several order of magnitude more demanding than the existing standards.
Also memory impacts the cost, power and performance of heterogeneous multi-processor architectures. The need for large amount of storage and a high bandwidth access to it comes from two ends. The primary need comes from the applications becoming more multi-functions and data intensive (high resolution, higher bandwidth communication etc.). The secondary need comes from the requirement to hide the latency of accessing slower off chip memory.
As such MOSART addresses novel architectures for multi-core computing systems in embedded systems, the project defines and develops the Software/Hardware design environment encompassing a flexible, modular, multi-core, on-chip platform, and associated exploration methods and tools, to allow the scaling and optimisation of various applications in multimedia and wireless communication.

Technical approach

MOSART addresses two main challenges of the prevailing multiprocessing architectures: the global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; and the difficulties in programming heterogeneous, Multi-core platforms, in particular, in many cores and in dynamically managing data structures in distributed memory.
MOSART aims to overcome these challenges through a multi-core architecture with distributed memory organization, a network-on-chip (NoC) communication backbone, and configurable processing cores that are scaled, optimized, and customized to achieve diverse energy, performance, cost, and size requirements of different classes of applications.
MOSART achieves this by providing platform support for managing abstract data structures, including middleware services and a runtime data manager for NoC-based communication infrastructure; and developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.

The mission of MOSART project is to define and develop an efficient SW/HW design environment encompassing a flexible, modular, multi-core, on-chip platform, and associated exploration methods and tools, to allow the scaling and optimisation of various applications in multimedia and wireless communication.
The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory.
MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by:
A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure;
B) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.
The aim is to maintain Europe as a worldwide player in the field of efficient implementation of MPSoC architectures. These ambitious goals are achievable because we bring advanced tools and platforms, i.e. a NoC platform and design space exploration tools from KTH, data management tools from DUT, middleware for NoC services from ART, parallelizing and mapping tools from IMEC, processor configuration tools from VTT. SMEs ART and COW contribute to tools, and two systems companies TCF and ICOM bring applications from future high data rate wireless access.

Campo scientifico

Programma(i)

Argomento(i)

Invito a presentare proposte

FP7-ICT-2007-1
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Meccanismo di finanziamento

CP - Collaborative project (generic)

Coordinatore

THALES SIX GTS FRANCE SAS
Contributo UE
€ 699 922,00
Indirizzo
AVENUE DES LOUVRESSES 4
92230 Gennevilliers
Francia

Mostra sulla mappa
Regione
Ile-de-France Ile-de-France Hauts-de-Seine
Tipo di attività
Private for-profit entities (excluding Higher or Secondary Education Establishments)
Contatto amministrativo
Gwenael GUILMIN (Dr.)
Collegamenti
Costo totale
Nessun dato

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Ultimo aggiornamento: 16 Luglio 2019

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Permalink: https://cordis.europa.eu/project/id/215244/it

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