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Compound Semiconductor Integrated Circuits

Objectif

This project involved six major European companies from three countries. The objective was to develop advanced GaAs integrated circuit technologies leading to the fabrication of high-performance integrated circuits addressing key memory and fast signal-processing functions. The availability of state-of-the-art GaAsICs will serve European system and equipment manufacturers in the IT and telecommunications industry and help to provide them with the necessary worldwide competitive edge.
The project was broadly divided into high-complexity ICs using enhancement/depletion mode MESFET logic (STC, LEP, and Siemens), and high-speed ICs using depletion mode based MESFETs and HEMTs (Thomson, Plessey and GEC). GaAs heterojunction bipolar transistors (HBT) were also included in the latter part of the project to complement the MESFET and HEMT technologies.
MESFET, HEMT and HBT technologies are in different stages of maturity, but many key technologies are shared, such as ion implantation, advanced lithography (Ebeam, deep UV and DSW), dry processing, selfalignment techniques and testing tools. These technologies were investigated in parallel, from device modeling to manufacturing capability.
The objective was to develop advanced gallium arsenide integrated circuit technologies leading to the fabrication of high perfomance integrated circuits addressing key memory and fast signal processing functions.

The project was broadly divided into high complexity integrated circuits (IC) using enhancement/depletion mode metal semiconductor field effect transistor (MESFET) logic and high speed ICs using depletion mode based MESFETs and high electron mobility transistors (HEMT). Gallium arsenide heterojunction bipoloar transistors (HBT) were also included in the latter part of the project to complement the MESFET and HEMT technologies.

Key demonstrators of increasing complexity were produced and some of those achieved state of the art performances:
low power consumption (220 mW) gallium arsenide IK static random access memory (SRAM) with access time in the range of 1.4 ns;
4-stage serial multiplier using self aligned technology which can be clocked at over 800 MHz, equivalent to 1.25 ns/bit multiplication time;
4:1 divider reaching 9.7 GHz clocking speed;
4-bit analogue to digital converter (ADC) capable of 1 G sample/s with on chip sample and hold and error correction functions, with performance equivalent to the best 0.6 micron silicon emitter coupled logic (ECL) technology.
Key demonstrators of increasing complexity were produced and some of those achieved state-of-the-art performances: low power consumption (220 mW) GaAs 1KSRAM with access time in the range of 1.4ns 4stage serial multiplier using self-aligned technologywhich can be clocked at over 800MHz, equivalent to 1.25 ns/bit multiplication time, 4:1 divider reaching 9.7GHz clocking speed, and finally, 4bitADC capable of 1Gsample/s with on-chip sample and hold and error correction functions, with performance
equivalent to the best 0.6micron Si ECL technology.
Exploitation
The technology developed under this project is being exploited in different ways by each company in the consortium. Some have transferred it into their pilot lines to improve their commercial products or to add new products to their catalogue. Others haveapplied the technology in broader areas of IIIV semiconductors, such as optoelectronic integrated circuits, and have helped to accelerate their research activities.
Finally, this project had led to over 40publications in international conferences and technical journals.

Thème(s)

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Appel à propositions

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Régime de financement

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Coordinateur

BNR Europe Ltd
Contribution de l’UE
Aucune donnée
Adresse
London Road
CM17 9NA Harlow
Royaume-Uni

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Coût total
Aucune donnée

Participants (6)