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Contenuto archiviato il 2024-04-15

Technology for GaAs-GaAlAs Bipolar ICs

Obiettivo

This two-year project was dedicated to the development of a basic process validated on HBTs and SSI divider (D/2 and D/4) ECL circuits and to the investigation of the specific steps of a future advanced self-aligned process.
The general objective was to develop a high-performance GaAs process using GaAs-GaAlAs HBTs for ultrafast emitter coupled logic. E-beam lithography, plasma deposition and etching techniques were investigated, together with all aspects of the IC process, including material epitaxy (both MBE and MOCVD), ion implantation, rapid thermal annealing, lithography, dry etching, ohmic contacts (including refractory alloys) and dielectrics. This work was accompanied by a strong effort in modelling, concerning both 1D and 2D device numerical modelling and analytical CAD block models.
The general objective was to develop a high performance gallium arsenide process using gallium arsenide/gallium aluminium arsenide heterojunction bipolar transistors (HBT) for ultrafast emitter coupled logic. Electron beam lithography, plasma deposition and etching techniques were investigated, together with all aspects of the integrated circuits (IC) process, including material epitaxy (both molecular beam epitaxy (MBE) and metal organic chemical vapour deposition (MOCVD)), ion implantation, rapid thermal annealing, lithography, dry etching, ohmic contacts (including refractory alloys) and dielectrics. This work was accompanied by a strong effort in modelling, concerning both 1-dimensional and 2-dimensional device numerical modelling and analytical computer aided design (CAD)) block models. Several approaches leading to selfalignment and micron and submicron rules were also investigated, with a very exciting successful fabrication of exploratory selfaligned HBTs. All 3 basic processes were characterised on HBTs with cutoff frequencies above 20 GHz and up to 29 GHz, and division by 2 and division by 4 circuits were demonstrated with input rates as high as 7.6 Gbits/s.
The most significant achievements were a high degree of quality and uniformity of both MBE and MOCVD layers, world-record values for ptype base doping, assembling, validation and comparison of three basic technological processes using ion implantation, r apid thermal annealing (RTA), dry etching, and high-performance ntype and p-type ohmic contacts (including the nonconventional InGeAu and AuMn alloys). Several approaches leading to selfalignment and micron and submicron rules were also investigated, with a very exciting successful fabrication of exploratory selfaligned HBTs. All three basic processes were characterised on HBTs with cutoff frequencies above 20GHz and up to 29GHz, and division by two and by four circuits was demonstrated with inputrates as high as 7.6Gbits/s.
Exploitation
A part of the HBT technological know-how developed during this project by CNET has been transferred to an SME, Picogiga, which is customising MBE epitaxial wafers.

Argomento(i)

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Invito a presentare proposte

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Meccanismo di finanziamento

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Coordinatore

Centre National d'Études des Télécommunications (CNET)
Contributo UE
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Indirizzo
196 avenue Henri Ravera
92220 Bagneux
Francia

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Costo totale
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Partecipanti (4)