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European platform for low-power applications on Silicon-on-Insulator Technology

Project information

Grant agreement ID: 216373

Status

Closed project

  • Start date

    1 January 2008

  • End date

    30 June 2011

Funded under:

FP7-ICT

  • Overall budget:

    € 870 602

  • EU contribution

    € 800 000

Coordinated by:

UNIVERSIDAD DE GRANADA

Spain

Project description

Next-Generation Nanoelectronics Components and Electronics Integration EUROSOI+ is a CSA project that upgrade the European network on silicon-on-insulator technology set up by the EUROSOI project.

     In the framework of FP6, the European Commission supported the formation of a European Network on Silicon on Insulator Technology, Devices and Circuits, whose main goal was to create a discussion forum for the exchange of ideas and results on the topic of Silicon-On-Insulator technologies in Europe, and to facilitate the synergy between research groups which enables the use of Silicon-On-Insulator (SOI) technology as an effective tool to push the limits of CMOS and prepare for post-CMOS. Today, EUROSOI network comprises more than 30 partners all over Europe, with expertise in all the fields of the SOI technology. EUROSOI network has already made possible a big part of this path by successfully organizing and achieving during the last three years an important number of events such as the EUROSOI roadmap and state of the art documents, workshops, training events, scientific exchanges. .
     EUROSOI+ is a coordination action (CA) project aiming at promotion, maintaining, follow-up and upgrading the activities and the network set up by the previous CA project EUROSOI. Important objectives are: i) Creation of a Permanent European School on SOI Technology; ii) Fostering and co-ordinating the initiatives and activities required to successfully face some of the challenges identified and listed in the updated EUROSOI+ Roadmap for the future. Creation of a consortium to elaborate new research project proposals addressing specific challenges identified in the Roadmap; iii) Development of a research-dedicated platform in order to address circuit design aspects, focussing on the advantage of SOI technology for Low Power applications. This platform will provide, through the integration at some point in EUROPRACTICE, prototyping and Multi-Projects-Wafers in SOI open to European research groups and Fabless Semiconductor companies (SMEs) using LETI SOI process. The long-term goal is to make SOI technology reachable to any European research group or fables Semiconductor Company in order to allow any circuit design to have the chance to become a SOI circuit using European technology.

Coordinator

UNIVERSIDAD DE GRANADA

Address

Cuesta Del Hospicio Sn
18071 Granada

Spain

Activity type

Higher or Secondary Education Establishments

EU Contribution

€ 363 301

Administrative Contact

Francisco Gamiz (Prof.)

Participants (8)

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM

Belgium

EU Contribution

€ 63 772

UNIVERSITE CATHOLIQUE DE LOUVAIN

Belgium

EU Contribution

€ 63 772

INSTITUT POLYTECHNIQUE DE GRENOBLE

France

EU Contribution

€ 73 563

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

France

EU Contribution

€ 91 357

UNIVERSITY COLLEGE CORK - NATIONAL UNIVERSITY OF IRELAND, CORK

Ireland

EU Contribution

€ 68 105

CHALMERS TEKNISKA HOEGSKOLA AB

Sweden

EU Contribution

€ 76 130

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS

France

UNIVERSITE JOSEPH FOURIER GRENOBLE 1

France

Project information

Grant agreement ID: 216373

Status

Closed project

  • Start date

    1 January 2008

  • End date

    30 June 2011

Funded under:

FP7-ICT

  • Overall budget:

    € 870 602

  • EU contribution

    € 800 000

Coordinated by:

UNIVERSIDAD DE GRANADA

Spain