Objectif The objective was the development of a bipolar technology for high-speed data and signal-processing products. The generation of bipolar technology in production at the start of the project was characterised by minimum feature size of 2micron, a delay tim e of about 350ps, and an integration level for gate arrays of about 2500gates. The project aimed at developing a technology with a minimum feature size of 1micron, a selfaligning transistor structure with delay times below 100ps, a multilayer metallisation technique of up to four layers, and an integration level of about 50Kgates. The new technology was intended to increase the 10Mips capacity of mainframe computers from 10 Mips to about 40Mips, and the signal-processing speed of telecommunications circuits from about 600Mbits to more than 2Gbits by the end of the project. It was intended to achieve the above objectives in three stages characterised by the following gate delay and power delay product: 200 ps and 0.4pJ; 100ps and 0.1pJ; less than 100ps and less than 0.1pJ. The objective was the development of a bipolar technology for high speed data and signal processing products.The project aimed at developing a technology with a minimum feature size of 1 micron, a self aligning transistor structure with delay times below 100 ps, a multilayer metallisation technique of up to 4 layers and an integration level of about 50 K gates.The first demonstrator, a 10 K gate array, was available on schedule. The device was characterised by the following features:minimum structure size (mask dimension) 2 micron;minimum metal pitch 6 micron;3-layer metallisation technique;self aligned base emitter structure;gate delay 200 ps;speed power product 0.4 pJ.The second demostrator, a 4 K random access memory with an access time of less than 5 ns, was demonstrated.As a complement to the memory development, a testchip was developed for 4-layer metallisation with a metal pitch of 4 microns. The concept development for the third demonstrator and its technology have been worked out. Key features are a packing density of more than 5000 devices per square millimetre, a delay time of 70 ps at 800 uA gate current and a power delay product of 40 fJ (single ended logic, 3 level series gating). The gate current was programmable in 3 power steps (200 uA, 400 uA and 800 uA). The demonstrator contained about 7 K gates and demonstrated a technology which would enable the realisation of 25 to 30 K gate arrays within a chip area of less than 150 square millimetre.The first demonstrator, a 10Kgate array, was available on schedule in mid-1986. The device was characterised by the following features: minimum structure size (mask dimension) 2micron, minimum metal pitch 6micron, 3layer metallisation technique, selfaligned baseemitter structure, gate delay 200ps, speed-power product 0.4pJ. The second demonstrator, a 4K random access memory with an access time of less than 5 ns, was demonstrated in March1987, three months ahead of schedule. The high performance of the second demonstrator's technology was mainly due to a reduced base width a nd reduced lateral dimensions using a 1.0micron stepper lithography. The metal pitch was decreased to 5micron including non-nested vias between the first and second metal layer. For the realisation of the second demonstrator, a 4-layer metallisation scheme was not needed. However, as a complement to the memory development, a testchip was developed for 4-layer metallisation with a metal pitch of 4microns. During the fourth year the concept development for the third demonstrator and its technology have been worked out. Key features are a packing density of >5000 devices per mm2, a delay time of 70ps at 800uA gate current and a power delay product of 40fJ(single-ended logic, three level series gating). The gate current was programmable in three power steps (200uA, 400uA and 800uA). The demonstrator contained about 7K gates and demonstrated a technology which enable the realisation of 25 to 30K gate arrays within a chip area of less than 150mm2. Exploitation The production of the ECLGate Arrays was started in a new pilot line at Siemens in the first quarter of 1987. These circuits were primarily intended to be used in advanced computers and have been made available for all other user companies. The results achieved with project281 have enabled Siemens to introduce (in September 1988) new design rules enabling a reduction of the speed-power product by about 40% and an increase in the packing density of approx 30% (OXISIIIH). This new gate array family provided a programmable speedpower product with three power steps where power dissipation amounts to 1 W per 1000gate functions. The complexity of these arrays varied from 1.5K to 13Kgate functions. The 13Kgate array has been available sinceSeptember1988. A number of new processing steps were introduced by Philips into their production in Caeu during 1988-1989 at the same time as the process transfer from 3 inches to 125 mm diameter (with a production level of hundreds of wafers per day, mostly mixed analogue-digital ICs for consumer applications and telecommunications). Champ scientifique engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringsignal processingengineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunications Programme(s) FP1-ESPRIT 1 - European programme (EEC) for research and development in information technologies (ESPRIT), 1984-1988 Thème(s) Data not available Appel à propositions Data not available Régime de financement Data not available Coordinateur Siemens AG Contribution de l’UE Aucune donnée Adresse Balanstraße 73 81541 München Allemagne Voir sur la carte Coût total Aucune donnée Participants (1) Trier par ordre alphabétique Trier par contribution de l’UE Tout développer Tout réduire Radiotechnique Compelectr. France Contribution de l’UE Aucune donnée Adresse 130 avenue Ledru-Rollin 75540 Paris Voir sur la carte Coût total Aucune donnée
