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Ferroelectric Layers for Memory Applications and Sensors

Objectif

Ferroelectric compounds such as the lead zirconate titanates (PbZrxTi1-xO3, or PZT) exhibit a range of physical properties of interest for different applications. In particular, they are characterised by a permanent, electrically switchable dielectric polarisation, which makes ferroelectric capacitors suitable for binary, non-volatile data storage.

The objective of FELMAS is to demonstrate the feasibility of making high-quality PZT films of sufficient quality for non-volatile memory devices and to integrate them with existing CMOS technologies.
The development of a ferroelectric technology has been largely completed. Capacitors with a film thickness between 0.1 and 0.4 um have been deposited on 10 cm oxidized silicon wafers. They can be switched for more than 1010 cycles at 5 V and for more than 1015 cycles at 1.5 V. This is very promising for low voltage (battery operated) applications. On the process development side, it has been shown that the structuring of the capacitors can be successfully done by dry etching techniques such as reactive ion etching. This enables production of high density memories and enhances the compatibility with silicon integrated circuit (IC) processes.

Considerable effort has been expended on the design of a test structure evaluation module (TSEM) containing a number of complementary metal oxide semiconductor (CMOS) and ferroelectric test structures, sensor structures, different memory cells and a small (256 bit) memory. The design is now complete.
Specific aims are to:

- develop and optimise thin-film PZT deposition on silicon substrates (10-15 cm in diameter) using two different methods (sol-gel spin coating form metal-organic solutions and metal-organic chemical vapour deposition)
- optimise the influence of composition, dopant type and concentration, processing conditions and microstructure on the switching properties of PZT films
- optimise standard Ti/Pt electrodes and develop electrodes with improved switching properties
- develop models for the switching, fatigue and retention behaviour of ferroelectric thin films
- develop viable processing techniques compatible with IC technologies
- design, process and evaluate test structure evaluation modules (TSEMs) to demonstrate the compatibility of ferroelectric and CMOS technologies, using 1.5 micron technology and including a memory device.
- perform a preliminary evaluation of the industrialisation potential and limitations of the ferroelectric technology
- evaluate deposited ferroelectric films for sensor applications.

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Régime de financement

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Coordinateur

NEDERLANDSE PHILIPS BEDRIJVEN BV
Contribution de l’UE
Aucune donnée
Adresse
Kastanjelaan, 1218
5600 MD Eindhoven
Pays-Bas

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Participants (6)