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TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS

TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS

Objective

Technology projections indicate that future electronic devices will keep shrinking, being faster and consuming less energy per operation. In the next decade, a single chip will be able to perform trillions of operations per second and provide trillions of bytes per second in off-chip bandwidth. This is the so called Terascale Computing era, where terascale performance will be mainstream, available in personal computer, and being the building block of large data centers with petascale computing capabilities. However, these smaller devices will be much more susceptible to faults and its performance will exhibit a significant degree of variability. As a consequence, to unleash these impressive computing capabilities, a major hurdle in terms of reliability has to be overcome. The TRAMS project is the bridge for reliable, energy efficient and cost effective computing in the era of nanoscale challenges and teraflop opportunities.
The International Roadmap for Semiconductors (ITRS) report indicates that the Metal Oxide Semiconductor devices (MOS or MOS like devices) will be ultimately scaled down below 10 nm in several years. The CMOS technologies after the 16 nm technology generation are called Late CMOS technologies and will include novel multigate device architectures and novel channel and gate stack materials. Reliability issues are expected to be exacerbated to in sub-10 nm CMOS technology.
Beyond-CMOS emerging technologies will reach device dimensions reduction below 5 nm utilising among others, nanowire transistors, quantum devices, carbon nanotubes, graphene, or molecular electronics. Both the Late CMOS and the Beyond CMOS technologies hold the promise of a significant increase in device integration density complemented by an increase in system performance and functionality. However, a dramatic reduction in single device quality is also expected, complemented by increase in statistical variability, severe reduction of the signal to noise ratio, and severe reliability problems. Therefore,alternative device solutions and computation paradigms need to be investigated to keep the technology evolution pace in such a challenging scenario. Memory cells and, in general, system architectures intended for nanotechnologies (both late CMOS and emerging devices) need to address the variability and reliability problem and should be capable of solving or at least largely alleviating it. In order to build reliable nanosystems, the TRAMS project addresses a specific variability and reliability-aware analysis and design flow as well as a hierarchical tolerance design. In such a tera-device multicore system the main idea will be to define countermeasure techniques at circuit and architecture design levels. The objective of this project is to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort.
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Coordinator

UNIVERSITAT POLITECNICA DE CATALUNYA

Address

Calle Jordi Girona 31
08034 Barcelona

Spain

Activity type

Higher or Secondary Education Establishments

EU Contribution

€ 860 889

Administrative Contact

VALENTI GUASCH BRULL (Mr.)

Participants (3)

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INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM

Belgium

EU Contribution

€ 590 900

INTEL CORPORATION IBERIA SA

Spain

EU Contribution

€ 498 785

UNIVERSITY OF GLASGOW

United Kingdom

EU Contribution

€ 499 400

Project information

Grant agreement ID: 248789

Status

Closed project

  • Start date

    1 January 2010

  • End date

    31 December 2012

Funded under:

FP7-ICT

  • Overall budget:

    € 3 430 029

  • EU contribution

    € 2 449 974

Coordinated by:

UNIVERSITAT POLITECNICA DE CATALUNYA

Spain