CORDIS
EU research results

CORDIS

English EN

Nanoscale Silicon-Aware Network-on-Chip Design Platform

Project information

Grant agreement ID: 248972

Status

Closed project

  • Start date

    1 January 2010

  • End date

    31 December 2012

Funded under:

FP7-ICT

  • Overall budget:

    € 4 117 601

  • EU contribution

    € 2 925 000

Coordinated by:

UNIVERSITAT POLITECNICA DE VALENCIA

Spain

Project description

Design of semiconductor components and electronic based miniaturised systems The objective of this project is to develop an innovative network-on-chip oriented design platform constituting a toolkit for the construction of NoC-based multi-core systems in nanoscale technologies The NaNoC project aims at developing an innovative design platform for future Network-on-Chip (NoC) based multi-core systems. This NaNoC design platform intends to master the design complexity of advanced microelectronic systems by enabling strict component oriented architectural design. A compositional approach to NoC design in future multi-core chips is out of the reach of current design methods and tools due to new design constraints. Requirements for co-design with high-level platform management frameworks facilitates a need for enhanced dynamism and flexibility in NoC composition (e.g., virtualization, power management, thermal management, application management). On the other hand, a higher degree of uncertainty originating from nanoscale integrated circuit fabrication technologies raises the need to build reliable systems out of unreliable components.The NaNoC design platform provides design methods and prototype tools to cope with both challenges and to make NoCs a mainstream interconnect backbone for effective system integration. The platform enables NoC component assembly at each layer of the design hierarchy. Therefore, design for manufacturability techniques and tools are developed to preserve yield in the presence of manufacturing defects and circuit performance/power variability.Above all, the NaNoC design platform fosters tight cooperation between system research, circuit design and process development by means of a silicon-aware decision making at each layer of the design hierarchy. In this direction, NaNoC not only provides a cross-layer approach to tackle composability challenges (e.g., physical design techniques for enhanced reliability combined with architecture-level techniques for fault containment), but also defines an exchange format for interoperability between design tools for cross-layer optimization. Interoperability between developed NoC design methods/prototype tools and mainstream design toolflows will also be pursued.

Coordinator Contact

JOSE Flich (Mr.)

Coordinator

UNIVERSITAT POLITECNICA DE VALENCIA

Address

Camino De Vera Sn Edificio 3a
46022 Valencia

Spain

Activity type

Higher or Secondary Education Establishments

EU Contribution

€ 513 763

Administrative Contact

JOSE ANTONIO PEREZ GARCIA (Mr.)

Participants (7)

iNoCs

Switzerland

EU Contribution

€ 495 960

INFINEON TECHNOLOGIES AG

Germany

EU Contribution

€ 127 200

INTEL DEUTSCHLAND GMBH

Germany

EU Contribution

€ 113 626

LANTIQ Deutschland GmbH

Germany

EU Contribution

€ 355 131

TEKLATECH A/S

Denmark

EU Contribution

€ 481 650

UNIVERSITA DEGLI STUDI DI FERRARA

Italy

EU Contribution

€ 412 050

SIMULA RESEARCH LABORATORY AS

Norway

EU Contribution

€ 425 620

Project information

Grant agreement ID: 248972

Status

Closed project

  • Start date

    1 January 2010

  • End date

    31 December 2012

Funded under:

FP7-ICT

  • Overall budget:

    € 4 117 601

  • EU contribution

    € 2 925 000

Coordinated by:

UNIVERSITAT POLITECNICA DE VALENCIA

Spain