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Silicon Quantum Wire Transistors

Project information

Grant agreement ID: 257111

Status

Closed project

  • Start date

    1 September 2010

  • End date

    31 August 2013

Funded under:

FP7-ICT

  • Overall budget:

    € 4 326 034

  • EU contribution

    € 3 150 000

Coordinated by:

UNIVERSITY COLLEGE CORK - NATIONAL UNIVERSITY OF IRELAND, CORK

Ireland

Project description

Nanoelectronics Technology SQWIRE develops industry compatible CMOS technology based on novel Si nanowire transistor structures.

The aim of the SQWIRE project is to develop a disruptive, industry-compatible CMOS technology based on novel silicon nanowire transistor structures. As has been demonstrated both theoretically and experimentally, nanowire MOS transistors can be fabricated at wafer level using silicon-on-insulator (SOI) substrates and these novel devices have shown electrical properties that are comparable or even superior to those of regular transistors. Two such novel devices are the Gated Resistor (a junctionless transistor simulated, prototype fabricated and patented) and the variable-barrier tunnel transistor (VBT, simulated and patented). To obtain industrial validation, fabrication routes will be developed for these devices on novel 300 mm SOI wafers with silicon film thicknesses of only 10 nm. These routes will be underpinned by process development targeting atom-scale control of the silicon film thickness across the wafer. Device performance will be characterised at die-level and evaluated in a statistically meaningful manner at wafer level. The extracted parameters will serve as the basis for the development of a compact model of the Gated Resistor devices, which can be used for further circuit design and the validation of advanced numerical simulations. The fabrication process for the first device (Gated Resistor) is less complex and more flexible than that of regular transistors. It has the potential of increasing yield and reducing the price of integrated circuits. Furthermore, the Gated Resistor offers the promise of superior scaling to sub-22 nm dimensions compared to regular transistors. In addition, the process can easily be implemented in semiconductor materials other than silicon. The second device (Variable Barrier Transistor) is capable of providing subthreshold slopes sharper than any conventional transistor. This permits one to reduce the supply voltage of integrated circuits, and hence their energy consumption.

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Coordinator

UNIVERSITY COLLEGE CORK - NATIONAL UNIVERSITY OF IRELAND, CORK

Address

Western Road
T12 Yn60 Cork

Ireland

Activity type

Higher or Secondary Education Establishments

EU Contribution

€ 690 851

Administrative Contact

Conor Delaney (Mr.)

Participants (9)

MAGWEL

Belgium

EU Contribution

€ 284 499

INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM

Belgium

EU Contribution

€ 363 006

UNIVERSITAT ROVIRA I VIRGILI

Spain

EU Contribution

€ 251 036

SOITEC SA

France

EU Contribution

€ 125 113

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

France

EU Contribution

€ 951 673

INSTITUT POLYTECHNIQUE DE GRENOBLE

France

EU Contribution

€ 289 424

INTEL RESEARCH AND INNOVATION IRELAND LIMITED

Ireland

EU Contribution

€ 194 398

UNIVERSITE JOSEPH FOURIER GRENOBLE 1

France

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS

France

Project information

Grant agreement ID: 257111

Status

Closed project

  • Start date

    1 September 2010

  • End date

    31 August 2013

Funded under:

FP7-ICT

  • Overall budget:

    € 4 326 034

  • EU contribution

    € 3 150 000

Coordinated by:

UNIVERSITY COLLEGE CORK - NATIONAL UNIVERSITY OF IRELAND, CORK

Ireland