Forschungs- & Entwicklungsinformationsdienst der Gemeinschaft - CORDIS

Final Report Summary - LAMAND (Large Area Molecularly Assembled Nanopatterns for Devices)

Executive Summary:
Scaling has driven the microelectronics industry for over 40 years and revolutionised information and communication technologies. Maintaining progress by the introduction of new technologies is an important challenge as extensions to UV-lithography may limit the feature size realizable at acceptable costs. Self-assembly techniques could provide alternative methodologies and the development of low cost, chemical based technology was the focus of the EU funded LAMAND (Large Area Molecularly Assembled Nanopatterns for Devices) project. This project aimed to develop the direct self-assembly of block copolymers into a scalable process for the manufacture of silicon devices as well as addressing other technologies where small feature size patterning might have impact. The LAMAND consortium consisted of 9 partners from 7 European countries, 6 from academia and 3 from industry, specialised in micro/nanoelectronics, polymer synthesis and nanomaterials.
Main Results
Nanopattening methodology was developed for the creation of sub 10 nm feature size patterns over large areas (up to 8”). Both line and pillar patterns were realized. These patterns were integrated into processes to allow pattern transfer to a substrate to create arrays of nanostructures of silicon, copper and germanium. In this work, a directed self-assembly techniques were integrated into manufacturing scale processes to realize functioning devices. We showed that chemically designed/tailored silsequioxane films could be coupled to a nanoiprint method to generate topographically ordered substrates to define precise pattern alignment and orientation. New, block copolymer materials of controlled structure, dimension and function were synthesized and patterns at these were defined. New metrology was developed to allow quantification of pattern defectivity. Novel plasma etching techniques were used to transfer the pattern to the substrate surface and the device performance demonstrated. Innovative characterisation techniques capable of studying both long and short range structure were developed.
a) The work has helped the EU to develop an international profile in this area
b) Valuable intellectual property has been realized in the semiconductor, food packaging, oleophobic surfaces and metrology areas.
c) The consortium has provided European influence in the technology roadmaps.
d) Exploitation of the intellectual property is being undertaken
e) The consortium has demonstrated academic leadership in the area of block copolymer self-assembly.
f) Some of the consortium members are participating in a EU proposal to implement these methodologies into wafer manufacturing.

Project Context and Objectives:
At the start of the project in 2010, the potential of block copolymer self-assembly (by a process known as microphase separation) was being seriously considered as a potential method of patterning surfaces at the nanoscale [1]. These patterns could be used to generate well-ordered structures at a surface of around 10-15 nm feature size and although they could be used for development of many applications there most obvious use was for generation of surface topography for development of nanocircuitry for the microprocessor industry [2]. At this time, the feature size possible was below that realizable by conventional 193 nm lithography [3] and offered the potential to extend the lithographic limitations below 25 nm pitch size. The need for an alternative technique was clear: a) conventional UV lithography was becoming ever more challenging and expensive because of the need for multiple patterning techniques (i.e. where consecutive lithographic steps are used to trim features), b) extreme UV (EUV) lithography was being developed but progress has been slower than might have been expected or hoped and c) techniques such as e-beam lithography were not well enough developed to provide an industrial scale technique at the required processing times [see reference 3 in the appropriate Emerging Materials and Lithography Chapters].
Self-assembly techniques have long been seen as an alternative form of surface patterning [4] and techniques such as nanoparticle self-assembly, colloidal mediated self-assembly and macrophase separation of polymers were amongst the methods being suggested. The advantage of a chemistry based method of generating well-ordered surface patterns was clear. These techniques could be rapid, as defined by the kinetics of molecular diffusion etc., but (and probably more importantly) were relatively inexpensive compared to lithographic methods which now represent up to 50% of the cost of a modern processor manufacturing fabrication facility (FAB). Despite the obvious advantages, little progress has been made in integrating these methods into manufacturing because they lacked the reproducibility and reliability needed for device manufacture. Further, whilst local ordering of self-assembled patterns was well proven there was scant demonstration of ordered pattern formation over wafer dimensions.
In Europe, the development of inexpensive self-assembly based nanotechnologies was being seen as critical not only for the semiconductor industries but also for development of other technologies requiring ultra-fine patterning [5]. Consequently, FP7 provided substantial funding for self-assembly techniques and industrial scale-up. The home-based European semiconductor industry was also sensitive to changes within the large American and Asian multinationals who operated FABS in the EU but their continued presence was reliant on cost implications and the ability of the EU to advance new technologies for application in this sector. It is, therefore, necessary for European scientists to be at the forefront of emerging self-assembly techniques and their integration into manufacturing.
Of all the self-assembly techniques being explored in the late 2000s, block copolymer based methods were emerging as the most likely methodology to be integrated into semiconductor manufacture [1]. Patterns could be formed relatively easily over large substrates and techniques such as graphoepitaxy (the use of topography to direct the self-assembly (DSA)) and chemoepitaxy (the use of pre-patterned surfaces for DSA) were being developed to allow not only orientation of the pattern (to the surface plane) but also alignment (to a surface direction) [6]. Thus, provided the assembled nanopattern had dimensional regularity in terms of feature size, spacing and arrangement, the precise position of any feature could be strictly controlled and this is an absolute requirement for any semiconductor fabrication process. Despite the promise of block copolymer techniques, European researchers were not in the vanguard of this work which was being led by American, Korean and Japanese scientists. In 2005 the number of papers published by European researchers citing block copolymer self-assembly was less than 7% of the total papers (Google Scholar statistics).
LAMAND was written to address this research gap and allow Europe to develop a significant profile in this area. It was specifically centred on translating academic research into exploitable industry technologies in the semiconductor and other industries. It was focussed on addressing a number of key technical challenges:-
a) Transferring work on small substrates to large, industrial scale samples.
b) Reducing pattern defectivity through implementation of pre-patterning techniques..
c) Maintenance of ITRS defined scaling requirements (feature size). To properly address this the project has to extend its work to look at novel polymer systems and new pattern formation techniques such as solvent annealing.
d) Synthesizing novel polymers at the required purity and scale.
e) Demonstrating that polymer patterns could be transferred to the substrate by conventional methodologies.
f) Development of metrologies to assess both pattern formation, pattern defectivity and pattern transfer to the substrate.
g) Ensuring the materials and processes were consistent with modern manufacturing requirements (in terms of both their potential integration into current manufacturing lines as well as the appropriate safety requirements).

The project also had a well-defined goal to raise the European research profile in this area and to advance science to realize exploitable technologies and provide pathways for industrial uptake for those technologies.

To address these challenges, the project was centred on a number of technical workpackages to allow exploitable technologies to be developed. The specific objectives of these are described in detail below.
Project Objectives
There were a number of objectives described in the Description of Work (DOW) to achieve for the 8 workpackages (WP) described in this project. These WPs ranged from synthesising the polymers, generating substrates for DSA, generating patterns, quantifying structural regularity and defectivity, pattern transfer and device characterization and demonstrating manufacturability.
• WP1 Formation of periodic polymer nanopatterns, pattern transfer and active pattern generation: The aim of this workpackage was to produce block copolymer nanopatterns over large areas and at low defectivity consistent with manufacturing demonstration goals.
1) The delivery of topographically and chemically patterned substrates by Intel, ICN and LTM
2) The delivery of aligned and orientated BCP nanopatterns within topographically patterned substrates
3) The generation of active nanopatterns

• WP2 Polymer synthesis and molecular functionalisation: The aim of this WP is to synthetize and supply BCPs that microphase separate and SSQ materials.
1) The delivery of some BCPs
2) The delivery of PS-b-PDMS (diblock and triblock) and poly(isoprene)-poly(pentamethyl disilylstyrene) (PI-b-PPMDSS) type BCPs
3) The delivery of functionalized BCPs
4) The delivery of Novel silsesquioxane (SSQ) based polymers
5) The delivery of Novel polypeptide synthesis through NCA approach
6) The delivery of DNA diblock polymers
7) The delivery of DNA triblock copolymers

• WP3 Substrate molecular functionalisation: This WP was to allow the chemical engineering of the substrate polymer interface to allow pattern orientation and large area coverage to be properly defined.
1) Delivery of clean and well-defined substrate surfaces for chemical functionalisation
2) Delivery of some Molecular functionalisation of surfaces

• WP4 Nanometrology development for self-assembled structures: The aim of this workpackage was not only to provide a robust characterization of the surfaces used but also to allow proper quantification of the patterns in terms of defectivity.
1) Delivery of a report on the use and development of techniques for the study of self-assembled structures (all partners)
2) The delivery of a report on sub-wavelength light diffraction techniques for scalable characaterisation of self-assembled layers
3) The delivery of a report on x-ray techniques for scalable characaterisation of self-assembled layers (UCC)
4) The delivery of a report on novel image simulation analysis methods for assessment of order, alignment and orientation of BCP thin films (ICN)
5) The delivery of a report on the e-characaterisation of active nanostructures (UCC /Intel) and on quantitative aspects of non-contact characterization of conduction pathways nanostructures by AFM (UNEW, M24)

• WP5 Large scale and 3D pattern formation : This WP was centred on developing the methods shown above on coupon (1 cm2) sized samples to wafer scale and to introduce additional pattern complexity without introduction of expensive multi-level processing.
1) To demonstrate graphoepitaxy with SSQ based resists (ICN, CNRS/LTM, UCC-TNI)
2) To show proof-of-principle of top down NIL (nanoimprint lithography) based graphoepitaxy and the development of multi-level interconnected structures (ICN, CNRS/LTM, UCC-TNI)

• WP6 Technological development and scale-up : To demonstrate technological development to industrial standards and advance science into industry ready technologies.
1) To validate materials for use in commercial processes (Intel, PRO, KAN) :
2) To report of successful large area wafer processing steps and in-line testability (PRO, CNRS/LTM, ICN, Intel, KAN)
3) To establish a roadmap for Large Area Molecularly Assembled Nanopatterns for Devices (Intel) : Task 6.3, corresponding to D6.3 (Intel, postponed from M30 to M33) D6.5 (Intel, M36)
4) To identify and exploit of near-term product opportunities (PRO, KAN, Intel, ICN, UCC-TNI, UOI)
• WP7 Project management:
1) To maintain the consortium agreements (UCC), by modifying it if necessary and informing the EU commission about proposed changes
2) To maintain the project office and project committee, and notify the EU commission of any changes in the consortium structure (UCC)
3) To management external relationship Task 7.3
4) To manage the financial aspect of the project (UCC)
5) To create and maintain the consortium website (UCC)
6) To manage the financial aspect of the project (UCC)
7) To ensure that interim reports are delivered in time (UCC)
• WP8 Intellectual Property Management : This WP was wholly necessary to manage advances be properly so that any intellectual property might be properly exploited within the consortium.
1) To ensure the capture and reporting of all forms of scientific output and to manage the use of the dissemination activities
2) To ensure that all valuable IPR and know-how is properly captured
3) To set up and maintain the project IP and commercialisation database
4) To manage a meeting/workshop for the wider scientific community in particularly regard to developing technological outputs by appropriate publicity and invitations so that routes to commercial exploitation might be developed
1. ‘Chemical Interactions and Their Role in the Microphase Separation of Block Copolymer Thin Films’, Farrell RA, Fitzgerald TG, Borah D, Holmes JD and Morris MA, J. Mol. Sci., 10(2009)3671-3712
2. ‘Large-Scale Parallel Arrays of Silicon Nanowires via Block Copolymer Directed Self-Assembly’, Farrell R A, Morris M A et al, Nanoscale, 4(2012)3228; ‘Scaling beyond lithographic limits – block copolymer self-assembly mediated sub-20 nm FET devices’, Morris MA in Nanotimes, News, p41, Aug. 2010
3. ITRS 2008 – 2012
4. ‘Self-assembled templates for the generation of arrays of 1-dimensional nanostructures: From molecules to devices’, Farrell RA, Petkov N, Morris M A and Holmes J D, J. Coll. Interface Sci., 349(2010)449-472
5. ‘The Semiconductor Industry : Review of the Sector and Financing Opportunities‘, H Gruber, European Investment Bank, 2001.
6. ‘Directed block copolymer self-assembly for nanoelectronics fabrication‘, D J C Herr, Journal of Materials Research, 26(2011)122

Project Results:
LAMAND represented a highly ambitious project geared to fulfil some key scientific and technical goals. At the start of the project, centres such as IMEC were beginning to explore how block copolymer (BCP) lithography could be scaled into a manufacturable methodology. During the course of the LAMAND project there was demonstration at both academic and industrial laboratories that the PS-b-PMMA system could be coupled with the chemoepitaxy techniques pioneered by Paul Nealey at Wisconsin/Chicago (see e.g. P Nealey et al, “Density Multiplication and Improved Lithography by Directed Block Copolymer Assembly”, Science 321(2008)936) to produce almost lithographic quality patterns. The PS-b-PMMA system is a good prototype for demonstration/integration since both PS and PMMA can be used within modern FABS, the polymers were relatively amenable to the Nealey based chemical pre-patterning techniques, well-ordered patterns can be formed relatively simply by thermal annealing and pattern transfer from these polymers to the substrate was established on the microscale. However, the pitch size realizable via PS-b-PMMA is relatively large in comparison to current and future scaling demands and the insertion of BCP lithography into manufacturing will require chemical modification of the system or the development of new polymer systems and processing methods. The scientific focus within LAMAND was to explore the limitations in BCP lithography and extend the PS-b-PMMA work towards the delivery of new polymers into a large area processing method. An idealized schematic of the scientific work programme is described below.

Here, polymer synthesis was as described in WP2 as the synthesis of BCPs (for pattern formation) and resist materials (for developing NIL masks to topographically pattern the substrate for DSA). Substrate functionalization relates to generating the correct chemistry at the surface to define high surface coverage and pattern orientation and was described in WP3. Surface engineering is the topographical patterning of the substrate to align patterns to a pre-defined topography and so confer feature registry. Both NIL of designed UV-sensitive polymer and more conventional silicon fabrication techniques were used (WP1 and WP5). Pattern formation is the realization of well-defined BCP patterns encompassing film deposition, film processing and pattern transfer to the substrate and was described in WP1. Pattern quantification centered on how these ultra-small feature size arrangements might be imaged and explored to provide a quantifiable measure of pattern control and defectivity (WP4). Finally, these techniques were combined in WP6 to show how these scientific developments could be combined into a process flow for development of manufacturing methodologies. Two distinct areas of work were explored. Firstly, integration into a conventional silicon fabrication process flow for delivery of ultra-small device structures. Secondly, we also explored how the methods might be scaled in a cost-effective chemical process for coating very large areas of substrates for non-electronic applications such as anti-microbial packaging. All these individual elements were successful and progress within each individually described objective (4.1.2) was clearly demonstrated. Key results in each of these areas is summarized below.
Polymer Synthesis
Several BCP systems were fabricated successfully. The aim of this work was to produce a series of polymers that provided the required phase separated nanostructure at the correct pattern dimensions. In several cases, commercial materials were available but in many instances (such as low molecular weight lamellar systems for ultra-small line patterns, polystyrene-b-polyethylene oxide was a suitable example) these were not available. These polymers were produced at high purity and low polydispersity allowing reproducible process methods to be developed. Typical examples are given in Figure 1. The ability to synthesize > 100g of polymers was a key advantage as many experiments to optimize processing were possible and this can be limited by the high cost of commercial materials.

Figure 1 : A, B, Orientation controlled PS-b-PDMS nanopatterns from a BCP manufactured in this work. C, variation of feature size with molecular weight for typical BCP. D, typical POSS materials produced here.
Another advantage of being able to synthesize BCPs was to be able to explore the minimum feature size that can be attained. This is determined by the molecular weight and chemical incompatibility of the blocks and has a lower value beyond which phase separation can not be attained. This is not possible with commercial systems because of the prohibitive costs. A typical example is seen in Figure 1C which allowed us to demonstrate scaling to sub 12 nm pitch (6 nm feature size).
The other notably successful polymer synthesis work was in the production of POSS (polysilsesquioxane) resists. Some of these are illustrated in Figure 1D These materials had an important function in LAMAND. We exclusively used graphoepitaxy to afford DSA of the patterns. Whilst a number of wafers were manufactured by silicon fabrication methods, their continued use would have been prohibitively expensive for pattern optimization. We this used nanoimprint lithography (NIL) to pattern substrates. This needed a UV curable resist so that a robust topography could be developed and the POSS materials were developed for this function. However, the work we carried out was elevated by the synthesis of POSS with different terminal organic groups. This allowed the surface chemistry (i.e. hydrophilic v hydrophobic) to be tuned to maximize pattern coverage and structural order. The work was so successful that we believe that both the POSS materials represent exploitable technology and further that the POSS-NIL based methods for topography generation could be used for delivery of block copolymer lithography to polymer substrates with the promise of generating printable logic circuitry.
Substrate Functionalization
The wetting of a polymer at a surface is partially controlled by the interfacial energies. For block copolymer systems there is also an interfacial energy determined preference for one block. This will frequently ordain pattern orientation. In lamellar PS-b of this -PMMA films, vertical alignment of the individual lamellae is only possible for ‘neutral surfaces’ where both blocks interact equally with the surface. This can be achieved by the attachment of a random copolymer brush to the surface. This requires synthesis of the polymers, their terminal functionalization and careful attachment procedures. The highlight of this work was the definition of simple small molecule procedures via gas or solution exposure to define the surface chemistry. These methods represent a facile, rapid and low cost method that could be used in industry. Typical results are shown in Fig. 2. Where an ethylene glycol brush at various coverages could be used to control pattern defectivity.

Figure 2: PS-b-PDMS patterns on silicon substrates following exposure to 1, 3 and 5% (L to R) ethylene glycol solutions. The pattern has been partially etched to show the structure.
Surface Engineering
In the graphoepitaxial technique the physical topography of a substrate surface is used to direct the block copolymer pattern to align with the topography. It is not a physical technique though. If, for example, we are using 2D channels as the aligning topography, it is the preferred interaction of the sidewalls with one of blocks that ordains alignment. However, the size and depth of the channels must be consistent with the BCP pattern dimensions. Further, the shape of the channels must be strictly controlled and uniform. Ideally, the size walls should be perpendicular to the surface plane. Substrate topographical patterning was critical to our success since his allows patterns to have the positional and directional accuracy needed for device fabrication.

Figure 3: SiN substrates ov varying topographical dimensions to form 1, 2, 3, 4 BCP line structures.
Two types of substrates were available to us. Firstly, we had silicon, silicon nitride and carbon coated which were manufactured by Intel using conventional UV-lithography. These proved extremely valuable as they consisted of pre-patterns that had spacings of various values that were highly accurate and were also varied on the nm scale allowing us to determine the optimum dimensions for a particular BCP. An example of these substrates is shown in Figure 3 where SiN topography dimensions were varied to control the number of BCP features in each channel.

Figure 4: The insitu graphoepitaxial method where a NIL stamp acts as aligning topography, a) and b) are typical patterns at different magnifications, c) a simple schematic and d) a photograph of the apparatus designed and built in the LAMAND project.
The second type of substrates used were manufactured in the project. Nanoimprint lithography (NIL) was used to make these substrates. NIL was viewed as an ideal laboratory method since it is significantly less expensive than alternative methods such as e-beam. The availability of these substrates allowed a large number of samples to be used for pattern formation and transfer process optimization. The major advance of the work, however, was that it provided a unique method to control the chemistry of the sidewall and channel base to allow ideal graphoepitaxial alignment and low defectivity. This work advantaged the range of functionalized POSS resists prepared here. The methodology was scaled and is described in more detail below. The NIL advances reached a level of maturity that allowed insitu generation of topography and pattern generation using techniques pioneered by us. The advantage of these techniques was that it could be used to minimize the number of process steps used in pattern formation. This is illustrated in Figure 4. In this method, the NIL stamp is imprinted into the BCP to pattern and align the BCP simultaneously. The apparatus built allowed polymers to be solvent annealed within the cell and in this way a number of individual process steps are carried out at the same time. Whilst this method might not be consistent with large scale silicon fabrication, it may have potential in other areas such as low cost printable electronics and substrates for applications such as biological media.
Pattern Formation
Pattern formation is, of course, at the heart, of the LAMAND project. Progress was dependent on the other work areas since we had to use synthetic polymers, engineered and functionalized surfaces. Many examples have already been provided above and more below. There were a number of objectives:-
a) To provide robust process conditions for a number of polymer systems
b) To provide polymer systems reaching very small feature size
c) To provide patterns of low defectivity
We worked on thermal annealing but because of need to move towards systems capable of ultra-small feature size, we had to develop solvent annealing methods. In solvent annealing, the polymer film is exposed to solvent vapours at relatively low temperature. Solvent molecules enter one or more blocks (depending on chemical affinity), increasing free volume and sponsoring polymer movement and allowing the systems to reach the minimum free energy as a microphase separated pattern. For the small dimension forming patterns, the blocks are very chemically different and the blocks have quite different glass transition temperatures and melting points and hence quite different mobilities at various temperatures. Thus, achieving high order can be problematical. Using solvent annealing, and e.g. selective solvent mixtures, block mobilities can be matched. An example of our progress in this area is represented by our use of microwave assisted solvent annealing. This has the advantage of decreasing process times from hours to the order of 1-5 minutes. A typical example is shown in Figure 5 where well-ordered patterns of PS-b-PDMS were formed under microwave irradiation in periods of around 2 minute.

Figure 5: microwave assisted solvent annealing as described in text. Patterns on various topographical substrates, dimensions as shown in figures.
The other aspect of the work worth noting particularly is the feature size reduction. Working with the polystyrene-poly vinylypyridyl (PS-b-P4VP) we were able to get to sub 16 nm pitch size. Typical data are shown in Figure 6. Using tehse systems we were able to reach a feature size of around 5 nm and demonstrate it can be pattern transferred to the substrate.

Figure 6: Phase separated BCP patterns from molecular weights of 10,000 (L) and 6,000 ® g mol-1 showing pitch sizes of around 15 and 11.3 nm.
Pattern Quantification
Characterizing these systems is critical and further proper quantification is pivotal in assessing their ability to intersect the demands of the semiconductor industry where low defect concentrations are a pre-requisite. Metrology for assessment of these patterns in terms of defining defect density, line-edge roughness, positional accuracy will need to be developed to assess the integration of new technologies into FABS as well as the ‘on-line’ characterization of manufactured wafers.

Figure 7: PS-b-PEO images. L, He ion microscopy images, M AFM images and R X-section TEM data
Two significant problems for metrology exist. The first is the image analysis used for examining very small feature sizes and, further, how 3D (i.e. through film) morphology rather than simple top-down information can be ascertained. On approach we have used is the possible use of helium ion microscopy (HIM), and within this project we have reported data using this form of analysis for the first time. HIM has a resolution between SEM and TEM. The advantage of using this technique can be seen in Figure 7 where HIM can be compared to AFM of a lamellar PS-b-PEO system of pitch around 14 nm. SEM and AFM are challenging and whilst AFM reveals phase separation, the lines are indistinct and broken. However, in HIM, well-resolved lines are clearly seen. The image is of sufficient quality to measure line roughness and interface effects. Also visible are some holes in the pattern which are due to partial removal of the hydrophilic PEO block and also some white defects which arise from carbon contamination during analysis. We have also pioneered TEM x-section imaging as also seen in Figure 7. This has required careful optimization of the FIB sample preparation. Seen above the film is a dark region which is dense Pt to protect the sample during the cut and above this particulate/crystallites of Pt. Clearly visible are PEO cylinders. This is the first image of its kind and shows that cylinders are ‘flattened’ due to in-plane film stresses.
The other area where the project has made a significant contribution to the science of BCP systems as well as providing significant intellectual property for exploitation is in developing software for image analysis allowing proper quantification of defects. Code was developed which allows a complete analysis of a pattern in terms of dimension, dimension regularity, pattern anisotropy and positional accuracy. It also allows an extensive analysis of specific defects such as dislocations, disclinations, missing elements and curvature. Additionally, the code is also capable of quantifying order and periodicity of the assembled structures, estimating line widths and line-edge roughness. These represent critical parameters for assessing pattern regularity for use in circuit manufacture. The advantages of this new software relate to its exclusive development for BCPs although it has relevance to the analysis of any surface pattern and might have industrial use for any lithographic process. It further reduces analysis times to a few minutes and can be used for large area analysis. Typical examples are shown in Figure 8 for both dot and line type patterns.

Figure 8: SEM images of linear patterns formed from self-assembled block copolymers: linear elements and defects identification and analysis. Red and green spots represent defects of various types.
Scale-up and demonstration
The ultimate success laid with integrating each of the individual work programmes into a process flow which could be used industrially and demonstrating the process flow across a wafer sample. These process steps can be identified:
1. sample cleaning: generation of a reproducible surface for subsequent treatments
2. topography formation: ultimately this was a lithographically carbon hard mask engineered substrate consistent with state-of-the-art nanodevice fabrication used industrially
3. surface functionalization: to affect high surface coverage and uniform polymer film deposition
4. polymer film deposition (PS-b-PDMS): by spin-coating using solvents consistent with industrial use
5. pattern formation: a solvent annealing process for which a prototype chamber allowing full process control was fabricated
6. pattern transfer: a state-of-the-art plasma etch process was developed for selective block removal and silicon pattern transfer

Images representing the advances are described in Figure 9. (A) represents the in-house manufactured carbon hard mask samples. SiARC is the carbonized silicon layer. (B) represents the first stage of pattern transfer where the PDMS cylinders are transferred into the SOC layer. The uniformity of the samples should be noted. Note that the original PS-b-PDMS pattern is converted into silica like lines by oxidation and hydrocarbon removal in other plasma etch processes. (C) is the second stage of pattern transfer where the pattern formed in (B) is transferred into the silicon substrate. (D) is a photographic image of the constructed solvent annealing chamber. Solvent annealing is an area which requires detailed attention for use in industry and the work here is a major step in the eventual uptake of this technique for BCP integration.

Figure 9: Scale up for PS-b-PDMS system

Potential Impact:
The scientific impacts of the project can be very briefly summarized:-
1) Around 50 papers from the project will have been published
2) Over 75 scientific presentations will have been presented at various national and international conferences and meetings
3) The academic groups involved in the project have significantly increased their scientific reputations:-
- The group have organized 2 international DSA meetings in 2012 and 2013. The latter one was held in the Euronanoforum meeting in Dublin and attracted 75 international participants
- The meeting in 2012 was attended by senior ITRS and SRC representatives and were testimony to the international reputation of the group
- M A Morris has contributed to the last two iterations of the ITRS Roadmap for Emerging materials; MAM will give an international WEBINAR on BCP lithography in October 2013
- Further international funding for work on etchless techniques has been provided by the SRC
- Cork have been invited to host a session at the Internationally recognized SPIE conference which is the most important lithography conference in the World. We have had acceptances from 6 of the most respected leaders in the field.
The industrial application and uptake of the methods in the semiconductor industry has been advanced through our DSA workshops and the ITRS engagement as well as direct interactions with Intel. As well as this, the LTM and Cork groups together with Intel are partners in a ENIAC pilot line proposal for delivery of BCPs for integration of technology into manufacturing lines. This proposal is led by Arkema and has reached the final phase of the applications.
Intellectual property has been developed and a number of patents have or about to be submitted. These are fully detailed elsewhere and are summarized here.
NANODOTS –A method for providing a nanopattern of metal oxide nanostructures on a substrate (Application No. 11189329-2222). This patent relates to using BCPs to generate a hard-mask which can then be used to produce high aspect ratio, hi-fidelity substrate patterns.

An antimicrobial food package (Application No. P10939EP00). This relates to the use of BCP nanopatterns to generate oxide and metallic nanodots which impart antimicrobial activity on a substrate.

Software image analysis. This is described above and relates to the new code for pattern quantification. It is believed to be highly valuable and a number of companies have expressed interest.

Sub-wavelength light diffraction techniques. These methods allow pattern quantification using light and is a complimentary technique to high resolution electron microscopy. Its value lies in being consistent with in-line analysis for manufacturing assessment.

Desk top multipurpose nano-imprint lithography module. This is an invention that allow insitu processing of polymer films and will have short term academic impacts and may be scaled for large area film processing.

Commercial impacts have been developed with some success. The work with Kanichi has allowed a simple cost effective technique for developing BCP patterns over very large areas consistent with the preparation of large rolls of materials rather than hard substrates. With this we have been able to progress further commercialization of the technologies developed here. The on-going commercialization work is briefly summarized.

Development of novel food packaging materials. Funding has been obtained for assessing the technology, the optimum route to market and a full consultancy report from an international expert. The work has been favourably received and further funding is now being applied for to develop prototype materials.
Development of oleophobic polymer films. Using techniques described here, super-hydrophobic materials can be produced at low cost. These substrates can be used for screens and displays that are resistant to dirt and grease.
We are also in discussion with one company on using these methods in light emitting diode applications but this is under a confidentiality agreement at the moment.
We are working with a chromatography company to pattern silicon for on-chip column applications and are currently testing the first prototype device.
In summary, we believe that the LAMAND project has made a very strong contribution to European science in this area and enhanced the EU reputation and allowed significant international impact. We have allowed the EU to be at the forefront of international work to integrate BCP techniques into large scale silicon device manufacture with pilot-line manufacture expected within 3 years. We assert we have developed valuable intellectual property which will be exploited by EU companies. The impacts have warranted the investment made in the LAMAND team and the advances and impacts have exceeded what might be expected from the level of funding.

List of Websites:
Project public website :
Lamand Logo :
List of beneficiaries :
Beneficiaries name Contact details
Tel. +353 21 4902180
Fax +353 21 4274097
Department of Chemistry, University College Cork, Cork, Ireland
School of Chemistry
University of Newcastle upon Tyne Bedson Building
Newcastle upon Tyne
United Kingdom
Tel: +44 191 222 6262
Fax: +44 191 222 6929

3. UNIVERSITY OF IOANNINA (UOI) Apostolos Avgeropoulos, PhD
Professor of Polymer Science
Department of Materials Science & Engineering
University of Ioannina
University Campus – Dourouti
45110 Ioannina
Tel: +30 26510 07387-8, 07316
Fax: +30 26510 07034

Tel. + +34 93 586 8304
Fax +34 935868313
Phononic and Photonic Nanostructures Group

5. SELCUK UNIVERSITESI (SU) Prof. Dr. Mustafa Ersoz
Department of Chemistry
Selcuk University
42075 Konya
Tel. (90) 3322412484
Fax:(90) 3322412499

Laboratoire des technologies de la microélectronique (L T M)
17 rue des Martyrs
38054 Grenoble Cedex 9
Tel. +33-4-38789292
Fax +33-4-38785892

7. INTEL PERFORMANCE LEARNING SOLUTIONS LIMITED (Intel) Jennifer McKenna, EU Research Project Manager
c/o Intel Ireland Ltd
Mailstop IR6-1-1
Collinstown Industrial Park
Leixlip, Co. Kildare, Ireland
E-mail :

Tel: +43(0)7252 885-406
Fax: +43(0)7252 885-101
Functional Surfaces and Nanostructures, PROFACTOR GmbH, Steyr-Gleink, Austria
David Killworth, Company CEO
tel +44 7802 788436
Email :
Beacon Management 33 Hough Lane, Wilmslow Cheshire SK9 2LH

Verwandte Informationen

Dokumente und Veröffentlichungen

Reported by

See on map
Folgen Sie uns auf: RSS Facebook Twitter YouTube Verwaltet vom Amt für Veröffentlichungen der EU Nach oben