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CHESS/CHECKERS: An environment for the design of heterogeneous processing systems

CHESS/CHECKERS is a CAD-environment that supports the design and use of programmable DSP processors and embedded DSP cores in heterogenous signal processing systems.
In the market of embedded systems, one can witness an increasing use of programmable processors to realize systems on chip. These processors offer field or mask programmability, and therefore support late specification changes, hardware reuse, and flexibility to add new features to the system.
This processor can take the form of either a general-purpose DSP licensed from a processor vendor and integrated on the IC together with customer-specific hardware, or can be an in-house designed application specific instruction-set processor (ASIP), offering more efficiency in terms of a power dissipation and silicon area. Both solutions currently suffer from a lack of supporting tools in the form of efficient software compilers.
The CHESS/CHECKERS environment supports both general-purpose DSP processors and ASIPs in the design of embedded systems.

CHESS is a retargetable compiler that translates a C source code programme into highly optimized machine code. The compiler copes with the architectural peculiarities of contemporary DSP processors. The computer can easily be retargeted to different processors by supplying a processor model defined in the processor description language nML.
CHECKERS is a retargetable instruction-set simulator, able to simulate the execution of machine code in a cycle and bit accurate way. It can either be executed in a stand-alone mode or be called from a VHDL simulator. Retargetability if achieved by the use of the same nML description as in the case of CHESS.
The CHESS/CHECKERS environment is being commercialized by the spin-off company Target Compiler Technologies NV.

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Target Compiler Technologies
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