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H2020

SEPHY Report Summary

Project ID: 640243
Funded under: H2020-EU.2.1.6.1.

Periodic Reporting for period 2 - SEPHY (SPACE ETHERNET PHYSICAL LAYER TRANSCEIVER)

Reporting period: 2016-05-01 to 2017-04-30

Summary of the context and overall objectives of the project

The growing complexity of space systems is creating the need for high speed networking technologies to interconnect the different elements of a spacecraft. This interest has spurred initiatives by both ESA and NASA to define the next generation networking technologies for Space. In both cases, Ethernet has been the preferred choice due to its wide adoption in terrestrial applications and because it is fully specified in standards to ensure interoperability.
The main objective of this project is the development of a radiation hardened 10/100Mbps Ethernet physical layer transceiver for the space market that could enable Ethernet based on technologies to become an international space standard in future applications. An additional objective is to study the feasibility of a Gigabit Ethernet physical layer transceiver for space as the natural evolution of the 10/100 one and also to make sure the future IEEE 802.3 standards over a single twisted pair take into consideration the space sector requirements.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

First year period summary
During the first year of the project most of the goals presented for this timeframe have been achieved however some activities have incurred in delays so the overall project planning has suffered a small deviation.
As the project kicked off, WP1 and WP8 started to run immediately taking care of the management and dissemination/exploitation tasks. Once the operating procedures of the project where closed, WP7 was launched to always keep an eye on the future roadmap and on the standardization activities related to SEPHY that were taking place. At that same time, the activity that took care of the gathering of system level requirements for the PHY development started (WP2). This work package was successfully closed in the Requirements Review meeting providing the project with a first analysis on the feasibility of SEPHY and the set of system level requirements needed to proceed to the next step of the development. WP3 started right away to provide a first approach to the overall PHY architecture as well as to draw the main guidelines to be followed on the future verification of the ASIC. The Architectural Design Review formally closed WP3 with a reference architecture and a verification procedure available.
Once WP2 and WP3 were closed, the actual PHY design started. In this first annual review only the design activities of the first phase were (and finally have) taken place. The goal of the phase 1 chip was to be able to prototype the most critical blocks of the Ethernet Transceiver, especially for 10BASET.
By the time the first annual review took place (30/04/2016) the available Multi Project Wafer fabrication windows had a slight modification w.r.t the ones originally conceived in the proposal so the phase 1 tape-out was scheduled to happen on 08/07/2016.

Second year period summary
During the first year of the activity the project suffered a small planning deviation mainly due to the alignment of manufacturing with the available fabrication windows. A new scenario was presented. Unfortunately, some test tasks required more time than planned so the testing of phase 1 will be extended as reflected in Figure 1.
The main goals of the project in this second year have been on one hand to manufacture and test the phase 1 chip (also referred as Test Chip 1 or TC1) and on the other hand to reach a high level of maturity on the final device so that the target manufacturing goal of TC2 could be achieved.
With respect to the first goal, the TC1 was successfully manufactured, assembled and preliminary tested for continuity and consumption with results in line with the expectations. In addition to that, a versatile and complex test setup has been developed to allow testing the TC1 in standalone mode (to validate the TC1 blocks) and also in system mode in combination with an external FPGA where the digital code that will be included on SEPHY’s TC2 could be preliminary validated.
Regarding the second goal, achieving a mature design of the phase 2 chip, it can be said that a huge effort has been put on this tasks both on the analog front end and the digital part.
In WP1 the overall coordination of the activities has taken place and two major milestones have been accomplished: the Preliminary Design Review and the Test Readiness Review of Phase 1. Extra management effort has been put in place to coordinate the interaction with external parties that have shown interest in the project, namely CERN, Airbus Defence and Space and Airbus Safran Launchers.
WP7 road-mapping activities have been focused on the analysis of a future implementation of a Gigabit Ethernet PHY covering the selection of the technology node and the estimation of circuit area and power for the different PHY options.
Finally, on WP8 a more in depth exploitation plan has been elaborated and many dissemination activities have taken place with the aim of getting SEPHY as much exposure as possible.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

The ambition of the SEPHY project is to put Europe at the forefront of the adoption of Ethernet PHYs in space systems. This goal is ambitious as 1) the Ethernet commercial and industrial IC market is dominated by non-European companies (Intel, Broadcom, Marvell, LSI, etc. and 2) Ethernet PHYs are complex mixed signal devices and there are no Ethernet PHYs qualified for space. Since the PHYs are a key component in Ethernet, the success of SEPHY would not only ensure non dependence but possibly also leadership position over other countries. Therefore the goals are ambitious both technically and in terms of the long term strategic impact of the project.

The SEPHY project also has the ambition to reuse the developed PHYs for other mission critical applications. Those include automotive, avionics and industrial systems in which Ethernet is already or is likely to be the dominant networking technology. This extends the ambition of the proposal beyond space systems. Extending the use of the SEPHYs for terrestrial applications could help in positioning Europe as a player in the Ethernet IC market (which is a large market with more than one hundred million devices sold every year).

The project also includes (in WP7) forward looking activities to enable the future development of a Gigabit Ethernet PHY for space. This work is highly innovative and involves the use of advanced signal processing, communications and electronics (analogue and digital). Also within this WP contributions to the Reduced Twisted Pair Gigabit Ethernet (1000BASE-T1, IEEE 802.3bp) standard will be made to make it suitable for space applications. This is a unique opportunity as this new standard will require only one twisted pair compared to four of the current standard (1000BASE-T). This will reduce the weight of the cabling which is an important factor for space systems.

Additionally, a study and implementation of advanced mitigation techniques for single events effects will be done in WP4.3. In particular, the research of UAN on fault tolerant signal processing implementations will be used to optimize the protection of the PHYs. This can result in lower costs compared to existing mitigation techniques. Additionally IHP will also investigate novel mitigation techniques at architectural level to improve the overall digital implementation reliability. Finally, UAN will also investigate on power efficiency in WP4.4 to provide a beyond state of the art PHY also in terms of power consumption.

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