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PowerBase Report Summary

Project ID: 662133
Funded under: H2020-EU.

Periodic Reporting for period 2 - PowerBase (Enhanced substrates and GaN pilot lines enabling compact power applications)

Reporting period: 2016-05-01 to 2017-04-30

Summary of the context and overall objectives of the project

PowerBase: Enhanced substrates and GaN pilot lines enabling compact power applications

Power Semiconductors are key drivers for the innovation capability of European industries, large and small, generating economic growth and supporting meaningful jobs for citizens
PowerBase aims to setup and enhance power semiconductor manufacturing pilot lines in the area of wafer production and chip embedding in packages with special attention on compact power applications. Demonstrators and full-scale testing are essential building blocks of the PowerBase project proposal meant to stepping up Europe's innovation capability by the development of technologies in the area of energy efficient systems. This will provide Europe with reinforced means to significantly raise its competitive edge across the economy and to address its key societal challenges. The project PowerBase aims to contribute to the industrial ambition of value creation in Europe and fully supports this vision by addressing key topics of both “Strategic Thrusts”: “Key applications” and “essential Technologies (capabilities)”. By positioning PowerBase as an innovation action a clear focus on the exploitation of the expected result is a primary goal.
To expand the limits in current power semiconductor technologies the following main goals will be targeted by the PowerBase project:
• Development of advanced carrier substrate technologies for improved GaN material quality and reliability for next generation GaN based power devices
• Setup of a qualified wide band gap GaN technology pilot line based on 200mm wafers for high performance normally off GaN power transistors including GaN-on-Silicon epitaxy with advanced process control, high manufacturing stability and yield
• Expanding the limits of today’s 300mm silicon based substrate materials for power semiconductors in two directions: First on the low ohmic substrates and second at high ohmic substrates by introduction of advanced doping materials and power device processes.
• Improving manufacturability in a high volume / high automated fab as being key for cost competitiveness: work on advanced automation
• Enhance system compatibility by introducing advanced packaging solutions out of a dedicated chip embedding pilot line
• Demonstrate results and reliability in leading compact power application domains
PowerBase expertise spans from raw material research, process innovation, assembly innovation and pilot line up to various application domains representing enhanced smart systems where size matters (portable devices, lighting, photovoltaic energy generation).

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

Objective 1: Innovation on advanced carrier wafer technologies for GaN devices (WP 1)
Several options for new carrier substrates have been investigated: In the past year the advantages and disadvantages of the different concepts have been explored by performing epi-growth, device processing and reliability testing. Finally, a selection could be made for two advanced buffer schemes and one for monolithic integration (detailed description in the milestone reports M1.4 & M1.5).

Objective 2: Expand the limits in ON resistance of low ohmic power transistors (WP 2)
In the second year the activities in WP2 were concentrated on improving the basic 300mm silicon substrates and device approaches through several learning cycles. In the low resistance Si substrate part the crystal growth process was optimised towards better stability and higher yields. For the low ohmic Power-MOS transistor device demonstrators are now available already showing comparable performance with the 200mm references. In parallel the characterization methods for the 300 mm silicon substrate and devices were further optimized and necessary control measurements were established

Objective 3: Provide reliability test methodologies and analysis tools for novel GaN power switches on advanced carrier substrates in new 3D integration (WP 6)
At device level, in workpackage 6 we developed methods for on-wafer fast reliability evaluation of time dependent degradation modes, as well as for hot electron effects. We also developed systems for in-system device testing adopting realistic conditions, and compared them to a standard JEDEC evaluation test suite. Advanced failure analysis techniques were also put in place.

Objective 4: Enable MtM solution for high variability (WP 4+5)
The single process developments of Objective 4.1 till 4.3 finished as planned. The decisions, which processes to be used in the pilot line have been taken. The usage of single processes also outside of the pilot line assessed and evaluated. In the last project year the single processes will be further optimized.
The second year was characterized by the final development and enhancement activities towards technology readiness of the More-then-Moore 3D processes. With the end of year two the integration processes for the pilot lines are started

Objective 5: Setup a pilot line for normally-on and normally-off GaN power devices (WP3)
The 150mm GaN normally-on base-line process in silicon fab is now fully established. All statistical process and defect density controls are installed. Improvements in wafer handling reduced wafer breakage and increased mechanical wafer yield to more than 90%. Process blocks such as gate module were further optimized resulting in stable electrical parameters. 150mm RFP GaN HEMT development was continued. A new gate module process was introduced leading to benchmark electrical results. First fully integrated runs of a normally-off pGaN power HEMT design were started

Objective 6: Enhance the compliance of GaN in standard packages and modules (WP 5+4)
The demonstrator design for embedding in mold compound pilot line was done, the assembly of the demonstrators started. The automation equipment for cleanroom usage has been analyzed (air flow concepts, filters), surface materials have been compared and Process Yield Detractors have been defined. Simulations of “PreDie” are ongoing and a simulation environment with a combined FE and BE design glow has been developed. For the Pilot Line for heterogeneous integration the line concept for the micro-hotplate released using DRIE etch and the line concept for 3D heterogeneous demonstrator was developed.

Objective 7 & 8: Achieve benchmark size and significant improvement in energy management (WP 7)
Based on the first Powerbase GaN devices the demonstrators for LED-lighting, solar inverter, battery charger and power supplies have been designed. Several test boards to be used for benchmarking measurements have been designed and de

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

After the second year PowerBase is even more convinced to be able to close the gap between research and exploitation and enable compact power devices for smart energy applications.
PowerBase is developing the next generation of ""energy-saving Chips"" and preparing them for mass industrial use in communication servers, lighting and renewable systems (and many other applications).
PowerBase will lay the foundation for a stable and achievable high volume production of GaN-Devices in and for Europe. Wide industrial use of GaN-Devices will become reality by proven reliability and price performance ratio of the devices.
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