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ANTI-CRASH: a surface compiler for temporal logic

With respect to complex embedded safety critical systems, especially for real time systems where system timing is crucial. a new compiler supporting a temporal surface language (TSL) has been developed which is suitable for describing hard real time safety critical applications. Called the surface compiler for temporal logic (SCTL), the technology translates the TSL into a classical logic language and the resulting logic description can be elaborated using existing classical formal verification tools. As specific rules of temporal inference are not needed, SCTL supports temporal information without increasing the complexity of the theorem prover, while also increasing the efficiency of model elaboration. SCTL is being integrated with high order formal tool (HOFT), an advanced verification tool under development.

SCTL allows real time hardware/software systems to be represented in a logical model using TSL, a typed logic language extended with special temporal basic primitives to deal with events, properties, time-points, and time intervals. SCTL translates a high order surface logic language into a first order platform logic language and the resulting representation, which has constraints instead of temporal operators, can be elaborated by a theorem prover engine, avoiding the use of specific inference rules for managing time operators. Using a higher order logic language allows both specifications and the corresponding implementations of system components to be formalized in a natural, compact, complete and readable manner. A formal verification tool can then be used to verify and validate the correctness and reliability of a system design with respect to its specification.

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