Community Research and Development Information Service - CORDIS

H2020

ExaNoDe Report Summary

Project ID: 671578
Funded under: H2020-EU.1.2.2.

Periodic Reporting for period 1 - ExaNoDe (European Exascale Processor Memory Node Design)

Reporting period: 2015-10-01 to 2017-03-31

Summary of the context and overall objectives of the project

The primary objective of ExaNoDe is to deliver a compute element, integrating core technologies that comply with the HPC system sizings and requirements for exascale computing. The compute element will be for prototype-level use by system integrators, software teams and subsequent evaluation though industrial deployment. Innovative nanotechnology and delivery mechanisms will be required for such a compute element, while researching and prototyping node-level software and validating its applicability across a relevant set of HPC application domains.
To accomplish this objective, ExaNoDe has sub-objectives for the Computing Element prototype and for the associated enabling software:
a) To design and document a highly integrated heterogeneous computing device for HPC applications.
b) The use and validation of 3D silicon-on-silicon level fabrication technology and advanced process geometry.
c) The integration of devices in-package with daughter-board including DRAM, local partition of primary storage and high-speed interfaces to the backbone interconnect.
d) The compute node is to be equipped with the necessary operating system and library support for resource sharing.
e) A specification for the integration of the compute node into a larger HPC system.
The objectives of the development of enabling software within ExaNoDe are to ensure the feasibility of applications with performances leading towards exascale. The design of the compute element and UNIMEM system architecture will lead to significant advantages for these frameworks to deliver performance and function to HPC applications. However, it is recognised by the consortium, that their fundamental designs may not be sufficient for the development of exascale applications. While it is beyond the scope of this project to develop the required enhanced libraries and runtimes for exascale applications, it is nevertheless considered essential to demonstrate the fundamental capabilities of the ExaNoDe platform through the enhanced support of current frameworks. The project will therefore port MPI to ExaNoDe’s UNIMEM-based architecture and evaluate and benchmark its latency and bandwidth. To enable the platform for future exascale-level applications, the operating system services, such as mmap and sockets, will also be enhanced to be integrated with the underlying ExaNoDe memory system capabilities. These capabilities will also be evaluated and tested by porting four different programming models in the project: MPI and GPI for inter-node parallelism and OmpSs and OpenStream for intra-node parallelism. Research will be undertaken into the runtime enhancements required to exploit the heterogeneous capabilities of the platform. This evaluation will use a set of mini-applications.
It is also important to document the various architectural elements and capabilities of the platform to enable future research and development of the software technologies and frameworks. This research and development is required to expose the full capabilities of the platform and as such enable access to the ExaNoDe technology in future system-level platforms.
In conclusion, and in terms of setting the overarching measurable objective of the ExaNoDe core technologies, this project will take the average of each of the deployment cost, the compute density, and the power consumption over the average of the top 10 of the TOP500 during 1H2016, and will target a 10-100 times improvement across all of these measures.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

During the reporting period it became necessary to revise the description of activities because no ARM V8-based compute chiplet, compatible with the active interposer, was available. This was due to commercial decisions by ARM’s industrial partners and because the primary backup plan of using the EUROSERVER chiplet was no longer possible due to changes within the EUROSERVER project. The lack of availability of suitable chiplets made it impossible to follow the initial DoA. The ExaNoDe project management alerted the Commission to this problem as soon as it became apparent in December 2015. Following significant discussion involving the ExaNoDe partners and the Commission, an interim review involving the Commission and external reviewers was held on May 26, 2016 and a check meeting on December 7, 2016, again involving the Commission and external reviewers. These meetings resulted in a revised DoA that was accepted by the Commission on December 21, 2016. Since the project developments were carried out in line with the changed workplan that formed the basis of the contract amendment, it is this version of the revised DoA against which the work during the reporting period should be evaluated.
The revision of the work plan is centred around changes in the design of the compute node. A summary of the basis of the revised approach is: the compute unit uses FPGAs with embedded ARM-v8 processors; FPGA configurable logic is used to support UNIMEM; 3D integration is maintained as an architectural vision and prototyped via the chiplet design, manufacturing and assembly onto a silicon interposer for chip-to-chip and multi-level global interconnect. This solution will support the original ExaNoDe architectural objectives and deliver prototype building blocks for systems approaching exascale.
The project has progressed the technical developments in line with the DoA corresponding to Contract Amendment. Work into the design of the Compute Node (figure 1) and of the prototype system (figure 2) has gone on in tandem with the application-oriented co-design work and the development of the enabling software layers. Details of the developments is provided in D1.1 “The Month 18 Management Report”. The project has progressed according to plan and hence will be able to realise the overall objectives, described above.
ExaNoDe is collaborating with the projects ExaNeSt and ECOSCALE, covered by a Memorandum of Understanding signed by the coordinators of all of the projects. This collaboration facilitates the exploitation of synergies between the technical developments of the three projects and enhances the impact of ExaNoDe.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

By targeting multiple technology advances, the project supports the future delivery of exascale-level computing systems and project results are to be transferred into the broader European programme for the delivery of exascale computing systems exploiting European technologies. This expected impact is thus fully aligned with the Strategic Research Agenda (SRA) of ETP4HPC and with the goal to increase European competitiveness in the semiconductor and HPC system markets. The energy-efficient architecture facilitates positive environmental impact, through the expected spread of exascale-level technology to standard off-the-shelf computing systems.
A summary of the key technology take-up items is as follows:
• Nanotechnology approaches that can deliver the required low-power, high density heterogeneous processor devices for the European ecosystem.
• The necessary software system to enable applications to exploit the enhanced scaling of the innovative, shared-memory paradigm, UNIMEM.
• New levels of compute density and resource convergence through the integration of compute, acceleration and IO within the system.
• Enhanced application and system resilience through a performance-maintaining virtualized environment.

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