Forschungs- & Entwicklungsinformationsdienst der Gemeinschaft - CORDIS

Mobile phone single chip circuitry

Mobile phones that are compatible with both the GSM/DCS and digital European cordless telecommunications (DECT) standards have been brought a step nearer by the integration of much of the necessary circuitry onto a single chip. The ASPIS processor comprises multiprocessor capabilities, including a custom DSP core for the signal processing functions of DECT and GSM/DCS; an ARM7 core for the protocols and overall system control; and a set of custom memory-mapped co-processors for interfacing to the various peripherals of the multi-mode handset. An application specific instruction-set processor (ASIP) approach was followed, in which, a novel digital signal processing (DSP) core was developed, optimized for low power dissipation, and with an instruction set tailored to the multi-mode terminal application. The ASIP approach also included a high-level validation step using a retargetable compiler, as well as an enhanced co-simulation/validation environment. Additionally, a new approach in hardware/software co-design, based on the provision of reusable object-oriented blocks was investigated. The development of the ASPIS processor with the ASIP approach shrinks the classical multi-chip implementations into a single chip solution. Also, the accompanying development methodology around the ASIP gives the warranty of early system validation, leading to a fast 'time to market' for the end product. Moreover, the adoption of a concrete methodology for implementing multi-functional DSP-based applications will be an important result for all industrial users.

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