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Reuse and quality estimation: advanced VHDL based design methodology for quick system development

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The result is a testability methodology and corresponding set of testability tools for use in the development of VHDL code. The testability methodology allows the designer to work with different levels of abstraction using appropriate techniques. The methodology and supporting testability tools have proved to be highly effective in terms of performance and reducing time for design recycle. The testability methodology defined, and the corresponding set of testability tools developed, allow the designer to take into account the problem of design testability from the entry-level of abstraction, without waiting for the gate-level description, where the solution to any testability problem heavily affects the other important design parameters such as area and performance. The testability methodology defined allows the designer to start from the behavioral VHDL description, thus identifying a level of testability measured as the expected gate-level fault coverage. This measure has been shown to be very close to the actual gate-level one. The designer is also able to identify redundant VHDL code and the VHDL parts which are more difficult to test, thus allowing the specification to be modified. Whenever the behavioural level is not available, but the design entry is an RT-level VHDL code, the methodology analyses separately the control part and the data part, applies different analysis techniques to identify the hard to test VHDL points, and provides possible functional design for testability solutions based on a partial scan-type approach. Finally, at gate level, test generation and redundancy removal tools for interacting finite state machines are provided, thus complementing the commercial test pattern generators available on the market, which are not able to efficiently deal with complex interacting finite state machines. The overall methodology has proved to be very effective in terms of size of designs analyzed, time saved avoiding design re-cycles, and results in terms of area and performance after the application of the proposed functional design for testability techniques. It is under test by the Italian telecom manufacturer which provided some of the benchmarks. Project URL : http://babbage.informatik.uni-oldenburg.de/research/request.html
CADENAS is a full-scan test insertion tool logic that replaces flip-flops in a hierarchical structural virtual hardware description language (VHDL) description. The main output of the program is another VHDL net-list with the test chains connected that can be used as input to an automatic test pattern generation (ATPG) tool for full-scan methodology The features of the program includes the following. A scan chain generation is based on a circuit floor-plan file, so that the arrangement of flip-flops and chains within the flip-flops is optimized to obtain a minimum area and speed impact the user may select not to include or modify some portions of the circuit. In this way, circuit modules that contain regular structures like memories and arrays etc are excluded. In the same way, modules that are to be tested with other test strategies may be left untouched. The program supports circuits with several clock signals. Additionally, the program allows the generation of individual clock lines for every scan chain. The program also generates a laser format flattened net-list file suited for its use with Platon, an ATPG tool. The tool is addressed to the foundry test generation phase of the digital application specific integrated circuit (ASIC) design flow. Its program runs on Sun Sparc stations with a SunOS 4.1 operating system.
Three virtual hardware description language (VHDL)-integrated common environment (ICE) navigation tools have been developed that fully integrated into the VHDL-ICE. The VHDL-ICE environment enables VHDL design units to be managed over heterogeneous and distributed computing environments. VHDL-ICE takes care of the dependencies at VHDL design unit and design entity levels. The navigation tools help the VHDL designer to develop and reuse VHDL descriptions corresponding to soft-cores. Using these tools it is possible to navigate through the design unit source code, the design hierarchy structure and the simulation model (statically and dynamically for debugging purposes The market for these tools, or more generally for the VHDL-ICE environment, is design teams involved in developing, maintaining and reusing soft cores. The key technical achievements introduced by these navigation tools is the possibility of offering access to the VHDL soft-cores intermediate information appearing during its processing for simulation purposes. Usually this information is hidden to the end-user and is only available for internal usage of tools such as VHDL simulation tools. The navigation tools offer end-users the possibility of exploiting this information, mainly for the purposes of reusing VHDL soft-cores.
PROTON is a tool that allows the quick and efficient checking of virtual hardware description language(VHDL) models against a coding standard. By automatically configuring generic design rule checks for VHDL code, PROTON ensures that all VHDL models are compatible with a given methodology and a given set of computer aided design (CAD) tools. By allowing VHDL coding standard rules to be programmed in a flexible and easy manner and by automatically configuring generic design rule checkers for these rules, PROTON can ensure that all VHDL models are compatible with a given methodology and a given set of CAD tools. This in turn guarantees that every designer uses VHDL in the same way. Being programmable means that methodologies can easily be redefined to cater for new criteria such as a change in the tools being used or in the general design flow. PROTON contains two separate tools: a rule specification tool that uses a simple input meta-language to specify the rules that define the coding standard (these rules are then compiled, and from this as many rule checkers as needed can be configured automatically.); a generic rule checking tool that accepts VHDL code and outputs error messages according to the compatibility between the code and the coding standard. It also optionally checks predefined quality rules and synthesis subset compliance. PROTON ensures that VHDL can be used as a true standard. The tools are aimed at design groups needing to verify that the VHDL models developed are compliant with VHDL design rules and guidelines imposed by corporate methodology, or by the tools used in the design flow.

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