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CADENAS: a full-scan test insertion tool logic

CADENAS is a full-scan test insertion tool logic that replaces flip-flops in a hierarchical structural virtual hardware description language (VHDL) description. The main output of the program is another VHDL net-list with the test chains connected that can be used as input to an automatic test pattern generation (ATPG) tool for full-scan methodology The features of the program includes the following. A scan chain generation is based on a circuit floor-plan file, so that the arrangement of flip-flops and chains within the flip-flops is optimized to obtain a minimum area and speed impact the user may select not to include or modify some portions of the circuit. In this way, circuit modules that contain regular structures like memories and arrays etc are excluded. In the same way, modules that are to be tested with other test strategies may be left untouched. The program supports circuits with several clock signals. Additionally, the program allows the generation of individual clock lines for every scan chain. The program also generates a laser format flattened net-list file suited for its use with Platon, an ATPG tool. The tool is addressed to the foundry test generation phase of the digital application specific integrated circuit (ASIC) design flow. Its program runs on Sun Sparc stations with a SunOS 4.1 operating system.

Reported by

Telefónica Investigación y Desarrollo
Emilio Vargas 6
28043 MADRID
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