Community Research and Development Information Service - CORDIS

H2020

NANOxCOMP Report Summary

Project ID: 691178
Funded under: H2020-EU.1.3.3.

Periodic Reporting for period 1 - NANOxCOMP (Synthesis and Performance Optimization of a Switching Nano-crossbar Computer)

Reporting period: 2015-12-01 to 2017-11-30

Summary of the context and overall objectives of the project

• What is the problem/issue being addressed?
CMOS transistor dimensions have been shrinking for decades in an almost regular manner. Nowadays this trend has reached a critical point and it is widely accepted that the trend will end in a decade. At this point, research is shifting to novel forms of nanotechnologies including selfassembled systems. Unlike conventional CMOS that can be patterned in complex ways with lithography, self-assembled nanoscale systems generally consist of regular structures. Logical functions and memory elements are achieved with arrays of crossbar-type switches. Here, the problem needed to be solved is “how to make efficient and high performance computing with nano arrays that includes logic synthesis, defect tolerance, and performance optimization?”, and it is the main motivation of this project.

• Why is it important for society?
The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New computing models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements both arithmetic and memory elements, necessitated by achieving a computer, by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of arithmetic and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of future and emerging computers beyond CMOS (current conventional computing technology).

• What are the overall objectives?
Research objectives:
The main objective of this project is developing a complete synthesis methodology for nanoscale switching crossbars that leads to the design and construction of an emerging computer. To achieve this objective, we follow a roadmap, with sub-objectives listed below.
1. Finding optimal crossbar sizes, modelling, and optimization: Fundamentally, all building parts of a computer, namely arithmetic and memory elements, use Boolean functions for their operations. Therefore implementing Boolean functions with optimal sizes significantly advances us toward achieving our main goal. Along with sizes, the main performance parameters power consumption, delay, and reliability values of crossbars will be achieved by developing related models. Performance optimization will be performed.
2. Implementing arithmetic and memory elements by considering reliability, area, delay, and power dissipation of the crossbars: We implement memory elements such as adders and multipliers, and memory elements such as flip-flops and registers as building blocks a computer. We also perform optimization for circuit performance parameters using the specifics of applicable technologies.
3. Realizing a nano-crossbar based synchronous state machine (SSM): By integrating arithmetic and logic elements as well as using technology parameters we realize a SSM as a representation of a computer that uses a complete logic flow and clocked control over state registration.

Additionally, as a communication objective we aim to introduce the project results to researchers worldwide as well as general public. Also as a training objective, we aim to experimentally learn fabrication needs and procedures for nano-crossbar arrays.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

By the end of the 24th month of the project covering the first periodic technical reporting, we have completed Work Package (WP) 1 and WP2. Also we have started WP3.

For WP1, plans have been overwhelmingly achieved; we have developed logic synthesis toolsto implements a given target Boolean function with an optimal or near optimal array/lattice sizes. Scientific contribution is much more than what was planned in the proposal. We publish 2 journal papers, 5 conference papers and a book chapter as opposed a planned 1 conference paper in the proposal. Additionally, as mentioned earlier, many extra dissemination and transfer of knowledge activities are performed although they were not planned in the proposal.

For WP2, all plans have been fully achieved. A defect tolerance technique as well as delay and power dissipation models of nanoarrays have been developed with determining trade-offs between the performance parameters. Scientific contribution is much more than what was planned in the proposal. We publish 4 journal papers and 7 conference papers as opposed a planned 2 journal papers in the proposal.

For WP3, so far we have performed 3 secondments, all to UMASS. we start investigating nano-crossbar technologies and technology parameters. Part of the research exploration has been published in 2 conference papers.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

Scientific excellence in the first 24 months:
• This project falls into the areas of emerging computing models and computational nanoelectronics. In recent years, the emerging research fields significantly attract attention that results in growing research and funding opportunities. Considerable amount of publications in top journals and conferences are about emerging research fields. Electronics engineering has no exception. With reaching its goals with top publications, this project contributes to the research excellence in electronics engineering including nanoelectronics in Europe. So far, we publish more than 15 peer-reviewed papers in leading journals such as IEEE and ACM journals and conferences such as DATE and ISVLSI in the area of nanoelectronics and computing.

Research to business and industry in the first 24 months:
• 8 secondments have been performed to our SME partner IROC in the first 24 months. Seconded staff have had a chance to perform active collaboration. Three joint papers demonstrate the effectiveness of these secondments.

Career development in the first 24 months:
• Quality of research and related publications is the main criteria for career developments in academia. This is valid for all levels starting from graduate students to full professors. Considering that the research conducted in this project is so fruitful with many high quality publications, the project’s help for career development of the project researchers is high. Note that overwhelming percentage of secondees and researchers in this project is from academia. Among the total of 15 secondees, 10 of them appear in publications or prepare/submit a publication.
• Secondments to the third country partners in USA offer the state-of-the-art research experiences for career development. For example, in the last two secondments to UMASS corresponding to WP3), we made an excellence progress on nano fabrication techniques, thanks to its state-of-the-art facilities.

Communication and dissemination activities in the first 24 months:
• We get involved in more than 20 activities to introduce our project, including 10 presentations of published conference papers, 2 demonstrations and exhibitions, 4 invited talks, 1 national workshop organization, 1 online showcasing in YouTube, 1 national magazine/bulletin column, and several university-wise department meetings/seminars.

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