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H2020

TAKEMI5 Report Summary

Project ID: 737479
Funded under: H2020-EU.2.1.1.7.

Periodic Reporting for period 1 - TAKEMI5 (Technology Advances and Key Enablers for Module Integration for 5 nm)

Reporting period: 2017-04-01 to 2018-03-31

Summary of the context and overall objectives of the project

In line with industry needs for the next generation Semiconductor technology for the manufacture of cost effective high performance logic ICs – Moore’s Law - the main objective of the TAKEMI5 project is to discover, develop and demonstrate lithographic, metrology, process and integration technologies enabling module integration for the 5nm node.
In lithography the aim is to optimize available EUV/NA0.33 scanners for mix & match with existing DUV/NA1.35 scanners, reducing overlay to less than 1.9nm.
Enable further chip size and cost reduction of the lithographic process a new “Hyper NA” EUV lithography tool will be developed which will reduce the minimum feature size and enable single exposure capability at the 5nm node.
In Metrology the objective is to create production ready metrology tools for application in the 5nm node. The key challenges are to improve resolution and enable multi-dimensional metrology capability for characterization of multi-dimensional structures and defects in “Under Layers”, that is beneath the surface of the chip.
In regard to 5nm process development the key objective is the development, evaluation and integration of process options that fulfill the 5nm node requirements in terms of performance, power, area and cost.

Work performed from the beginning of the project to the end of the period covered by the report and main results achieved so far

In Lithography alignment modules have been developed by ASML to improve matching between the DUV and EUV scanner systems. First overlay results are in the order of 2.4nm across the platforms which is well on track in regard to achieving the 1.9nm target.
The Hyper NA EUV system feasibility phase has been completed resulting in a preliminary system design specification, along with the integration plan. For the realization of the Hyper NA EUV mirrors numerous innovative techniques have been developed. Concepts for mirror metrology, mechatronics and production have been finalized and the realization has started. Corresponding heavy machinery has been delivered to Zeiss and installed in the newly constructed production facility.
IMS has defined the specification parameters and measurement techniques for the X-large Diffractive Optical Element (DOE) for mirror qualification in close cooperation with Zeiss. In parallel, first evaluations of the 17” DOEs have been done and a process that fulfils most of the specification parameters was found. Further investigations to resolve issues with asymmetric profiles at the edge of the substrate have been carried out and resulted in three solutions to resolve this issue which be focused on in the next period.
In metrology, the main focus is on the development of underlayer metrology and defectivity capability, work in this area is ongoing at Applied Materials Israel, Nova, Semilab, KLA-Tencor Israel, FEI and TNO. The techniques involved are Scanning Electron Microscopy (SEM) defect review tool, Scanning Transmission Electron Microscopy (STEM), X-ray Photo-emission Spectroscopy (XPS), Optical dark field, Enhanced Raman and Scanning Probe Microscopy (SPM). Analysis of void type defects in underlayers have started at Applied Materials and TNO. The main results achieved are the development of an accurate under layer mapping navigation flow for defectivity and overlay analysis and the development of a new STEM detector.
For process technology mask sets have been prepared in accordance with 5nm node. Subsequent technology development covered the validation of the patterning options, the process development and module built (morphological) of; “tall” FinFET and Gate All Around devices. High-chi Direct Self-Assembly technology for sub 20nm pitch Lines and Spaces using both organic-organic and Si-containing Block Co-Polymer (BCP) platforms, Scaling Boosters in which a Buried Power Rail (BPR) and Self-Aligned Gate Contacts (SAGC) have been assessed for introduction in 5nm node. In regard to interconnect an innovative sub10nm metallization scheme has been worked on including its morphological and electrical demonstration. Device integration is scheduled for year 2.

Progress beyond the state of the art and expected potential impact (including the socio-economic impact and the wider societal implications of the project so far)

All developments in this project are geared to move the capability of the industry to produce high performance semiconductor ICs beyond the present state of the art, in fact enabling the Semiconductor Industry to migrate to the next technology node following Moore’s law.
In lithography for example there is the design and implementation of new concepts for optimal mix and match in the use of Deep UV/NA1.35 and Extreme UV/NA0.33 lithography scanners has led to explicit advances. The application of new overlay matching approaches, both in hardware and in software implementations has resulted in an improvement in overlay from well over 3nm cross product overlay (state of the art) to 2.5nm.
In parallel to this, modules for an EUV-based lithography scanner are designed with major changes in the scanning system in order to support new exposure sequences and improvements in many sub-systems to match the requirements of the next technology node, such as stage technology, lens-, wafer-, and reticle heating technology and focus technology.
The NA 0.55 projection lens as developed by Zeiss is central part of the projection optics of the Hyper NA lithography tool, which is required to further increase the resolution of a EUV scanner. The underlying innovative imaging concept overcomes the limitations of 3D mask effects at high NA.

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