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Resist benchmarking methodology and results

A resist benchmarking procedure as well as a resist specification list have been defined within the UV2Litho consortium and this procedure was lined up with other consortia. This benchmarking procedure uses different masks (BIM, 6%attenuated PSM and alternating PSM) and illumination conditions and includes the following topics: resolution, profiles, process windows, linearity, substrate compatibility, pitch linearity, bright field versus dark field imaging, CD SEM shrinkage, Line-edge-roughness, delay stability, PEB sensitivity, etch resistance.

The procedure has been applied to benchmarking of 157nm resists at first on micro-steppers (at Selete, ISMT) and in a 2nd phase of the project on the ASML MSVII full field scanner. The goal of the resist benchmarking was to accelerate the resist development and to identify resist processes for exposure tool qualification (ASML MSVII at IMEC at first and for the ASML AT1600 under development) and for integration for the 65nm node. Partners potentially benefiting from these results are the semiconductor manufacturers who want to implement 157nm resists in production, resist suppliers and tool suppliers. All benchmarking results have been communicated to the partners in the UV2Litho process.

Continuous feedback has been given to the resist suppliers (non-project partners) on the performance of their materials in order to allow them to adapt the formulations according to the industrial specifications and available tools. Current status of the resist benchmarking: A large number resist materials have been screened and benchmarked according to the defined procedure. This has allowed a continuous assessment of the performance of 157nm resist throughout the project. Steady improvement in imaging performance of fluorinated resists has been observed. Imaging performance of current 157nm resist satisfies the resolution requirements for the 65nm node when using higher (0.85) NA scanners.

However, still significant improvements are required towards the 32nm node for which 157nm immersion lithography is a possible candidate. Besides imaging performance, improvements in resist contrast, Line-edge-roughness, etch resistance, delay stability and photospeed are necessary. The feasibility of a gate patterning process (litho and etch) using these 157nm resist in combination with a hard mask has been demonstrated.

As 157nm lithography is not going to be implemented for the 65nm node, the current available benchmarking results will not have an immediate application. However, the benchmarking methodology can easily be adapted to be applied for evaluation of resists for 193nm (immersion) or EUV lithography. If, the interest in 157nm (immersion) lithography would revive after 193nm immersion, the current resist results can be used as a guideline for resist development and optimisation towards the 32nm node.

More information on the UV2LITHO project can be found at:

Reported by

Interuniversity MicroElectronics Center (IMEC)
Kapeldreef 75
3001 Leuven
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