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Design of a flexible channel encoder

An FPGA-based flexible convolutional encoder has been developed which supports power saving by shutting down unused parts through specific enable logic. In order to cover a wide range of convolutional codes there should be a certain number of polynomials generated simultaneously. The memory of a single encoder will be 10, and we have chosen up to 16 data streams that can be emitted in parallel or, by proper configuration, can be joined to form code rates of 1/c; c = 2&16.

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