Wspólnotowy Serwis Informacyjny Badan i Rozwoju - CORDIS

System C/VHDL co-simulation tool

The co-simulation interface developed in the workpackage 2 of the project uses the Synopsys SystemC" front-end also developed in the ODETTE project in the context of the Workpackage 1 (synthesis engine).

The interface has been designed to accept a broad range of simulator interfaces and can thus work with different languages (VHDL Verilog) and commercial simulators.

The co-simulator tool developed and evaluated in ODETTE is part of a much broader Synopsys product, Synopsys CoCentric System Studio. CoCentric System Studio is a SystemC" based design environment, including simulator and specification environment for the verification and analysis of algorithmic, architectural, hardware, and software models at multiple levels of abstraction. System Studio provides as outputs executable specifications of the design, simulation data, and synthesizable SystemC" RTL hardware models. Particularly, CoCentric SystemC" Compiler accepts behavioural and RTL SystemC" descriptions and generates gate-level netlists for rapid prototyping of FPGA or ASIC hardware.

Further developments will be performed to improve the interface performances for large designs as well as improve the co-simulation between SystemC and SystemVerilog for Transaction Level Models (TLM).

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