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Formalization of an enhanced design flow including OSSS synthesis, System C/VHDL co-simulation and CoCentric system studio environment for rapid FPGA prototyping

The formalization of the design flow that has been described in D1.5, is a SystemC"-based synthesis flow. It includes the OFFIS OSSS synthesis tool, Cocentric System Studio environment and finally the Xilinx flow to reach the FPGA implementation level. CoCentric System Studio provides as outputs synthesizable RTL hardware models in VHDL and Verilog and constitutes the link between the high-level-models in OSSS and the FPGA synthesis environment.�

Regarding exploitation, this design flow can be partitioned in two parts: OSSS modelling (OFFIS synthesis tool) SystemC" modelling (Synopsys and Xilinx flows).

The exploitation that we foresee for the former is based on a follow-up possibly IST research project that can implement the required enhancements and optimisations. Siemens MC is available for a continuation of these research activities, providing models in SystemC" Plus and SystemC and formalizing and using a design flow that includes synthesis (with Synopsys System Studio, or other behavioural synthesis tools that may be available on the market in future) and FPGA flow to reach the implementation stages and evaluate the final results of the design activity.

The latter will be exploited internally under commercial agreements with Synopsys and Xilinx.

In the next year, research projects internal to Siemens MC and in cooperation with consultants, such as Politecnico Milano and Cefriel, will make use of CoCentric System Studio for synthesis-based research activities connected to FPGA design flow.

Moreover an agreement between Siemens MC, Synopsys and Xilinx is in place in
Italy in order to exploit the synthesis flow for an innovative targeted platform belonging to the Xilinx Virtex-II Pro family. This family enables designers to implement embedded processor-based applications with large flexibility using also IP cores and customized modules.

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