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Neural network with MVL weight assessment

An assessment was carried out to determine the potential of RTD based circuit topologies in VLSI architecture such as an FPGA, which is often used as a means of implementing neural networks. This particular application was chosen as it demonstrates very well the important issues facing VLSI chips such as: the drive to maintain (in line with Moore’s law) functional density/capacity, the high proportion of metal to device area due to interconnection conductors, propagation delay and power consumption. The core functionality of FPGAs is derived from SRAM based LUTs whilst the architecture can be configured for different application domains.

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