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Fabrication of cantilevers on CMOS substrates by EBL

A nano-resonator system has been fabricated directly on a pre-processed CMOS chip. The system is to be used for high sensitivity mass sensing applications in air and vacuum. The resonator system, corresponding of a cantilever and structures for electrostatic actuation and capacitive read-out, have been defined by electron beam lithography on top of a charge and radiation sensitive CMOS layer in predefined areas as a post-process step, without affecting the pre-processed CMOS circuits.

The subsequent etching steps to fully release the cantilevers have been obtained without stiction to the substrate. Cantilevers are driven at their mechanical resonance in a lateral mode, and the frequency is monitored by capacitive read-out on the chip. CMOS integration enables signal detection directly on the chip, which radically decreases the parasitic capacitances. Consequently, low-noise electrical measurements with a very high mass sensitivity are obtained. Fabricated resonator systems were characterized to have resonance frequencies of approximately 1.49MHz, which is in good agreement with a theoretical estimation of 1.41MHz. The theoretical mass resolution, m/?f, is approximately 17ag/Hz, using a Young’s modulus value of 160GPa.

The fabrication of the mechanical cantilever is performed as a post process module on pre-fabricated CMOS chips. Cantilevers are fabricated out of the bottom poly-Si layer (defined as the nanoarea). The poly-Si thickness is roughly 600 nm and underneath is a 1 m thick sacrificial SiO2 layer. A double layer positive resist system is deposited on the CMOS chips by spin coating. The bottom layer consists of approximately 170 nm of ZEP-520A7 and the top layer consists of 70-80nm of PMMA 950 A4.

Following the EBL exposure, the resists are first developed in a mixture of methylisobutylketone/isopropanol (MIBK:IPA; 1:3) and then in o-xylene with a final rinse in IPA. Then a 30 nm thick Al layer is thermally evaporated and lifted-off to be served as an etching mask.

After the lift-off, anisotropic reactive ion etching (RIE) is performed in order to transfer the EBL made pattern to the structural poly-Si layer. The anisotropy is achieved with SF6:O2 plasma.

After structural patterning, the poly-Si structures are to be released from the substrate by an isotropic wet etch of the SiO2 layer, using buffered hydrofluoric acid (BHF). First, the CMOS chips are spin-coated with 2.5 m of the photo resist AZ 5214E. The photo resist acts as a protection mask for the CMOS circuitry against the BHF. Next, ultra violet lithography (UVL) is used to create windows over the structural areas after which the chips are placed in BHF. Finally, the chips are thoroughly rinsed in de-ionized water followed by a dry release sequence.

In order to avoid stiction of processed nanocantilevers to the substrate or other surfaces, a dry release process is used. The dry release method is based on solidification of a supportive photoresist film followed by oxygen plasma removal. During rinsing of the BHF the de-ionized water is replaced by acetone, which dissolves the resist protection mask. Stiction is prevented by gradual substitution of the acetone with standard photo resist until the liquid covering the sample is concentrated resist. The resist covered sample is then spin-coated and soft-baked, resulting in a resist layer fully encapsulating the suspended nanocantilevers. The cantilevers are dry released using oxygen plasma ashing. This circumvents the process related stiction for releasing suspended nanostructures since there is a direct transition from solid state to gas state without the possibility of meniscus formation.

Reported by

22100 LUND
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