Community Research and Development Information Service - CORDIS

An alignment method for nanoimprint lithography based fabrication of nanostructures on a pre-processed CMOS chip

Several methods have been shown to be able to produce cantilever structures on CMOS chips i.e. EBL, AFM lithography and laser lithography. However, these are all serial and this would be a considerable limitation for industry production. NIL is inherently a parallel process. The objective here is to show that is possible to use nanoimprint lithography on a pre-processed CMOS chip.

In our standard stamp manufacturing process we use thermally oxidized Si 1 wafers, with an oxide layer thickness of 300 to 800nm. Electron beam lithography (EBL) and a metal lift-off process defines the stamp pattern and creates an etch mask for the consequent reactive ion etching (RIE), yielding a structure height of 100 to 400nm. After this we apply an anti-sticking monolayer (F13-TCS) on the surface of the stamp by CVD and the stamp is ready to use.

The alignment is made ex-situ in a Karl Suss (KS) contact mask alignment machine. It features micrometer screws and microscope with 50 and 200 times magnification. The precision is in the micrometer range.

Some minor hardware modification has been done. An alignment process has been developed, which include e.g. transport from the KS to the NIL machine.

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22100 LUND
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