Wspólnotowy Serwis Informacyjny Badan i Rozwoju - CORDIS

The Implementation of large scale spiking neural networks on reconfigurable hardware

Based on a reconfigurable hardware platform, a method for implementing large scale Spiking Neural Networks was created. The approach is based on the I&F conductance model and includes a form of Spike Time Dependant Plasticity (STDP) for on-chip learning.

Analysis of the logic requirements demonstrate that large scale implementations are not viable if a fully parallel implementation strategy is utilised thus an alternative approach where a trade off in terms of speed/area is made and time multiplexing of the neuron model implemented on the FPGA is used to generate large network topologies. To compensate for this speed performance compromise, optimised simulation strategies such as activity based and event based simulation were employed.

The final system is capable of simulation networks with up to 53,892 neurons and 53,892,216 STDP synapses. The system has been verified using SNN networks to perform 1D and 2D co-ordinate transformation and implementation results demonstrate significant performance increase over a PC based simulation. As a reconfigurable hardware platform was used the system is also flexible in terms of the neuron model used and it is also relatively easy to implement various network topologies and connection strategies.

Powiązane informacje

Reported by

University of Ulster
Intelligent Systems Engineering Laboratory, Magee College, University of Ulster, Nortland Rd.
BT48 7JL Derry
United Kingdom
See on map
Śledź nas na: RSS Facebook Twitter YouTube Zarządzany przez Urząd Publikacji UE W górę