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Ultra low power diode, memory cell and charge pump in thin film fully-depleted SOI CMOS 2µm process

A new family of ultra-low power (ULP) circuits has been developed and patented based on multi-threshold voltage MOSFETs and the reverse ULP diode concept. These have now been fully experimentally verified on UCL fully depleted SOI CMOS process up to elevated temperatures.

The basic advantage of the ULP circuit family is to achieve a much lower static power dissipation than standard MOS circuits, by biasing the n-MOS (resp. p-MOS) transistors in static operation (i.e. stand-by) at a gate-to-source voltage lower (resp. higher) than zero and hence a much lower leakage current.

Indeed, when compared to the classical MOS diode, the new ULP diode features a much lower reverse leakage current. Based on the ULP diode,

- The ULP memory cell has been proven to yield reduced static consumption, and better high temperature behaviour than standard six-transistor SRAM. The ULP memory functionality has been tested up to 280°C.

- A voltage doubler based on Dickson’s charge pump architecture has been designed either with a standard MOS or ULP diodes. Under high temperature conditions, the ULP charge-pump operates much better, demonstrates a much resistance to low clock frequencies and a much better efficiency than the standard MOS circuit.

Furthermore, the concept has been extended to data node keepers in MTCMOS low-power digital circuits. In circuits with idle or stand-by modes which disconnect unused parts of the logic for minimizing static power consumption, a drawback is the loss of the information stored on internal floating nodes. This requires the introduction of additional keepers or special flip-flops. Our ULP solution minimizes their inconvenience with regards to associated timing and area overheads.

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