Community Research and Development Information Service - CORDIS

High temperature failure modes in SoI

An important factor in ensuring product reliability is the effectiveness of the test strategies developed to identify defective circuits. In developing an effective test strategy is necessary to understand how various defects, which for example occur in the manufacturing process, affect the electrical behaviour of the circuit so that fault models can be created.

These fault models are subsequently used by design automation tools to generate effective and efficient test patterns to detect the presence of defective circuits. Applicability of fault models for low and high temperature testing must also be considered in this instance.

The result of the survey indicated that since a generic CMOS process is being used for both memory and logic circuits, although implemented in SoI, will, in general, be susceptible to similar fabrication defects as occur in logic/memory circuits implemented in standard bulk CMOS, hence will be detectable using current and voltage test methods.

For high temperatures the main failure mechanisms to be considered are electromigration, time dependent dielectric breakdown and “hot-electron” effects. However, it has been noted that time dependent dielectric breakdown and “hot-electron” effects are not too dependent upon temperature leaving the main failure mechanism to be due to electromigration which manifests itself as either a short or an open circuit, which can be detected using current and voltage test methods.

Success Factors:
- Understanding of failure modes will ultimately enhance reliability.

End Users:
- Designers for microelectronic systems to be used in HT applications in automotive, aerospace, oil exploration etc
- Manufacturers of semiconductors for HT applications.

Related information

Reported by

University of Newcastle upon Tyne
School of Electrical, Electronic & Computer Eng, Merz Court
NE1 7RU Newcastle upon Tyne
United Kingdom
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