The SoC architecture used in this project to implement the demonstrator chip is relatively complex requiring the application of diverse strategies, both for production and field test of the memory and logic blocks. In many SoC designs the capacity of the memory blocks is such that they occupy in excess of 50% of the chip area and consequently the incorporation of BIST (Built in Self Test) incurs negligible area overhead.

However in this instance the capacity of the memories is very small, amounting to two 32 x 16 and two 256 x 16 bit memories, consequently the design of a low area overhead BIST scheme is not only of paramount importance but also very challenging.

In order to reduce area overheads a shared BIST scheme has been adopted in which the BIST Controller, Timing Generator and Address Counter is shared. The resulting area overhead is only approximately 10%.

A BIST architecture to test the logic core has also been developed; initially using commercial tools incurring an area overhead amounting to 24%. However, an in-house scheme has been developed, namely BLTSCAN, which is also compatible with Boundary Scan Standard IEEE1149.1 and incurs an area overhead, which is approximately 50% less.

The outcome of implementing this built in meomory test scheme would be of interest to IC design houses, IP core designers, SoC and SiP designers; particularly if they are using small embedded memories.