Forschungs- & Entwicklungsinformationsdienst der Gemeinschaft - CORDIS

Final Report Summary - FRESH (From electric cabling plans to simulation help)

The FRESH project aimed to design a specific and innovative recognition methodology to lead to an automatic generating system in order to offer an alternative methodology compared with manual methods adopted in aircraft electrical harnesses. The specific objectives of the project were the following:
- to convert electric wiring plans into Computer-aided design (CAD) wiring diagram language;
- to translate CAD-generated wiring language into a universal language;
- to adapt and improve available software to transfer wiring diagrams (in a universal language) into electrical harnesses;
- to simulate electrical harnesses' physical behaviour and benefit from simulation verification and optimisation capabilities

The above-mentioned objectives would lead to:
- reducing electrical harness development costs;
- producing an error-free intervention level;
- reducing harness modification, maintenance and overhauling costs

The project succeeded in the following:
- the setting up of a recognition system of paper wirings further to the specification established by the end-user: adaptive threshold, image segmentation, and symbol identification were achieved. Integration into CAD and design of semantic knowledge were finished and validated. The prototype was presented during the Bourget air show and the final meeting;
- the development of modules necessary to reconstruct requested information related to electrical harness: the PIVOT universal language was specified and the tool of conversion for CATIA files was developed;
- provision of graph layout and the auto-routing algorithm was carried out. Orthogonal algorithms and heuristics were developed for the provision of automatic graph layout. The implementation of an interface on several pages and a friendly insertion of man-machine interface of harness into CAD software was improved, validated and finished;
- all models were created using the pack Elec simulator. A VHDL interface was developed and the model circuit analysis was fully specified. The new interface which allowed associating several models to a class of components was validated.

Verwandte Informationen

Reported by

Folgen Sie uns auf: RSS Facebook Twitter YouTube Verwaltet vom Amt für Veröffentlichungen der EU Nach oben