Community Research and Development Information Service - CORDIS

FP7

ESL_STR — Result In Brief

Project ID: 223819
Funded under: FP7-PEOPLE
Country: Greece

Helping software engineers choose the right hardware

Software developers often have limited expertise in the area of hardware and system architecture design. A novel tool is bridging the gap between desired functionality and hardware implementation.
Helping software engineers choose the right hardware
Electronic system-level (ESL) design is an innovative semiconductor development and verification methodology that has great potential to aid software developers with automatic design of hardware modules from the high-level representation of a task. However, the language tools required to communicate among the various layers of abstraction are largely lacking resulting in increased time to market.

Scientists sought to exploit stream and data parallelism processing paradigms enabling an application to be seen as multiple individual computational units (kernels) without explicitly managing communication among those units. EU funding of the project 'Automatic hardware generation using the stream programming paradigm' (ESL_STR) enabled them to achieve their goal. The case study was application to a field programmable gate array (FPGA), a semiconductor device that can be 'programmed' by the user (in the field) after manufacturing, rewiring the integrated circuit on the chip itself to produce the desired functionality.

Researchers produced a computer-aided design (CAD) tool to generate the co-processor design for an FPGA. The tool employs Open Computing Language (OpenCL), an industry standard programming environment to write programmes for heterogeneous computing architectures (those with more than one processor) consisting of the host or central processor unit (CPU) and the device or graphics processing unit (GPU). ESL_STR's version, called silicon OpenCL or SOpenCL, maps the parallelism (multiple processors) of an application onto a reconfigurable FPGA. A high-level compiler (HLC) partitions an OpenCL application's kernels across the CPU, GPU and the FPGA itself. A low-level compiler (LLC) processes the kernels selected to run on the FPGA platforms, generating an equivalent hardware design that fulfils performance requirements.

The ESL_STR tool opens the door to code portability across different multi-processor platforms, including both fixed and reconfigurable architectures. Such capability promises to make novel technologies such as FPGAs major players in the high-performance computing game.

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