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Breaking the speed barrier in semiconductors

Combined in situ measurements during semiconductor manufacturing revealed for the first time the cause of surface defects that limit device processing speed. This development paves the way to next-generation high-speed computing.
Breaking the speed barrier in semiconductors
Gordon Moore, Intel co-founder, predicted in the 1960s that the number of transistors on a chip would double approximately every 24 months. Known as Moore's Law, it essentially established the business model for the semiconductor industry whose exponential growth continues today. However, quantity is losing ground to quality, measured by performance in this case, given the push toward smaller and more powerful electronics.

Optimisation of speed in complementary metal–oxide semiconductor (CMOS) circuits beyond a certain level requires new materials with higher electron mobility than silicon (Si). The most promising are compound semiconductors based on materials in Groups III-V, including gallium arsenide (GaAs), indium gallium arsenide (InGaAs) and indium phosphide (InP). Integrating them into Si CMOS technology has been challenging due to the creation of a sort of electron mobility barrier between the channel and the gate dielectric as a result of imperfections in the semiconductor surfaces.

Atomic layer deposition (ALD) of aluminium oxide (Al2O3) instead of silicon oxide (SiO2) as the interface with the III-V semiconductors has yielded the most promising results. Nevertheless, defect density is still much larger than for SiO2/Si interfaces. Scientists initiated the EU-funded project 'Clustered atomic layer deposition for emerging microelectonic applications' (CALDERA) to develop combined and simultaneous in situ measurement techniques for greater understanding of defect production during deposition processes. Researchers employed scanning tunnelling microscopy, scanning tunnelling spectroscopy and synchrotron X-ray photoelectron spectroscopy never before combined in a single in situ (avoiding all exposure to air) analysis of the same sample.

Techniques enabled researchers to determine that defect generation on the InP surface was due to surface oxidation. Thus, cost-effective manufacture of high-performance InP devices for high-speed computing will require the elimination of all sources of oxidation, including exposure to ambient air throughout the entire device fabrication process.

CALDERA provided the first combined in situ analysis of the ALD Al2O3 deposition process, clearly revealing the source of surface defects leading to the decreased performance of transistors. Armed with such knowledge, manufacturers can overcome previous barriers to increasing the speed of transistor switching operations for big impact on tomorrow's high-speed computing applications.

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