Application specific processor and instruction set

Projektinformationen

ASPIS

ID Finanzhilfevereinbarung: 20287

Projekt abgeschlossen

Startdatum 1 Dezember 1995

Enddatum 31 Juli 1999

Finanziert unter

• Specific research and technological development programme in the field of information technologies, 1994-1998

Gesamtkosten € 5 600 000,00

EU-Beitrag € 2 800 000,00

Koordiniert durch

Intracom Sa, Hellenic Telecommunications and Electronics Industry
Greece

Exploitable results

CHESS/CHECKERS: An environment for the design of heterogeneous processing systems

CHESS/CHECKERS is a CAD-environment that supports the design and use of programmable DSP processors and embedded DSP cores in heterogenous signal processing systems. In the market of embedded systems, one can witness an increasing use of programmable processors to realize systems on chip. These processors offer field or mask programmability, and therefore support late specification changes, hardware reuse, and flexibility to add new features to the system. This processor can take the form of either a general-purpose DSP licensed from a processor vendor and integrated on the IC together with customer-specific hardware, or can be an in-house designed application specific instruction-set processor (ASIP), offering more efficiency in terms of a power dissipation and silicon area. Both solutions currently suffer from a lack of supporting tools in the form of efficient software compilers. The CHESS/CHECKERS environment supports both general-purpose DSP processors and ASIPs in the design of embedded systems. CHESS is a retargetable compiler that translates a C source code programme into highly optimized machine code. The compiler copes with the architectural peculiarities of contemporary DSP processors. The computer can easily be retargeted to different processors by supplying a processor model defined in the processor description language nML. CHECKERS is a retargetable instruction-set simulator, able to simulate the execution of machine code in a cycle and bit accurate way. It can either be executed in a stand-alone mode or be called from a VHDL simulator. Retargetability if achieved by the use of the same nML description as in the case of CHESS. The CHESS/CHECKERS environment is being commercialized by the spin-off company Target Compiler Technologies NV.

Mobile phone single chip circuitry

Mobile phones that are compatible with both the GSM/DCS and digital European cordless telecommunications (DECT) standards have been brought a step nearer by the integration of much of the necessary circuitry onto a single chip. The ASPIS processor comprises multiprocessor capabilities, including a custom DSP core for the signal processing functions of DECT and GSM/DCS; an ARM7 core for the protocols and overall system control; and a set of custom memory-mapped co-processors for interfacing to the various peripherals of the multi-mode handset. An application specific instruction-set processor (ASIP) approach was followed, in which, a novel digital signal processing (DSP) core was developed, optimized for low power dissipation, and with an instruction set tailored to the multi-mode terminal application. The ASIP approach also included a high-level validation step using a retargetable compiler, as well as an enhanced co-simulation/validation environment. Additionally, a new approach in hardware/software co-design, based on the provision of reusable object-oriented blocks was investigated. The development of the ASPIS processor with the ASIP approach shrinks the classical multi-chip implementations into a single chip solution. Also, the accompanying development methodology around the ASIP gives the warranty of early system validation, leading to a fast 'time to market' for the end product. Moreover, the adoption of a concrete methodology for implementing multi-functional DSP-based applications will be an important result for all industrial users.