Final Report Summary - SMARTAMS (Digitially Assisted Integrated Analog Mixed Signal Systems)
The project was set out to solve the challenges in CMOS analog mixed signal circuits and systems by attempting to alleviate the imperfection of analog components worsening as processes scale down by using signal processing algorithms and system level architectures. Existing solutions heavily depend on classical analog design methods that consume power and area. Mixed signal circuits designed in this fashion do not get scale down in size and are unreliable. This research is targeting to use cheaply available digital circuits and signal processing to solve problems caused by analog imperfections such as mismatch, dynamic glitches, non-linearity, clock phase errors, etc. The objectives are:
* Develop system level architectures that increase the immunity of the overall signal chain to analog errors thus reduce cost of analog and external devices
* Develop cost effective signal processing algorithms that attack analog mismatch and dynamic errors that hamper the system performance severely and create heavy process, voltage and temperature variations
* Develop mixed signal design methods and procedures the ensure analog performance from the beginning and increase reliability of mixed signal device
* Develop accurate mixed signal modeling environment using off-the-shelf simulation tools (e.g. Matlab & VHDL) that capture and simulate the potential pitfalls at the system concept design and test the effectiveness of the above proposed methods.
During the first period:
1. We built Matlab and Simulink models with accurate representation of circuit non-idealities such as analog mismatch errors, dynamic switching errors, glitch energies that create inter-symbol-interference specially in DACs, cross-talk and interference and memory effects, amplifier saturation, clipping limited band-width and quantizer metastability.
Main Results: This part provides fast and yet accurate simulation method early in system level design and enables to test and compare the impact of algorithms and architectures.
2. We developed an advanced signal processing algorithm to shape analog mismatch and inter-symbol interference errors simultaneously. The digital algorithm is implemented on FPGA board and we used a standard multi-level current steering digital-to-analog converter implemented in 45nm CMOS process.
Main Results: The algorithm is tested and verified extensively to deliver impressive results with virtually tone free analog to digital converter for audio applications. This digital implementation can be configured for any size DAC in any process with similarly perfect linearity results. These results are published in two papers as reported in Section 7
3. We are working on high order sigma-delta ADC design method with noise-transfer-function optimization to ensure stability and performance for extended input amplitude ranges. This eliminates the need for expensive and inefficient analog methods such as overload detection and integrator clamping in high order sigma-delta ADCs.
Main Results: Early results are very promising that resulted in system level design of a 7th order sigma-delta converter that is stable at almost full input swing with more than 6dB SNR improvement over competitive methods. We also defined novel stability measures and optimized for maximum stability while keeping performance at target range. A journal paper related to this work is under preparation
4. We are building on the earlier proposed Cascaded-Modulator Architecture that is used to reduce the out-of-band noise in DACs. This method can be improved by combining segmentation principle to increase DAC resolution and reduce out-of-band-noise further with the same cost or reduce the cost of mismatch shaping for the same noise resulting in better power and area efficiency.
Main Results: This research is still early in the investigation stage. Basic mathematical model predicts significant gains in out of band noise reduction for the same DAC area. Further modeling and simulation is needed
* Develop system level architectures that increase the immunity of the overall signal chain to analog errors thus reduce cost of analog and external devices
* Develop cost effective signal processing algorithms that attack analog mismatch and dynamic errors that hamper the system performance severely and create heavy process, voltage and temperature variations
* Develop mixed signal design methods and procedures the ensure analog performance from the beginning and increase reliability of mixed signal device
* Develop accurate mixed signal modeling environment using off-the-shelf simulation tools (e.g. Matlab & VHDL) that capture and simulate the potential pitfalls at the system concept design and test the effectiveness of the above proposed methods.
During the first period:
1. We built Matlab and Simulink models with accurate representation of circuit non-idealities such as analog mismatch errors, dynamic switching errors, glitch energies that create inter-symbol-interference specially in DACs, cross-talk and interference and memory effects, amplifier saturation, clipping limited band-width and quantizer metastability.
Main Results: This part provides fast and yet accurate simulation method early in system level design and enables to test and compare the impact of algorithms and architectures.
2. We developed an advanced signal processing algorithm to shape analog mismatch and inter-symbol interference errors simultaneously. The digital algorithm is implemented on FPGA board and we used a standard multi-level current steering digital-to-analog converter implemented in 45nm CMOS process.
Main Results: The algorithm is tested and verified extensively to deliver impressive results with virtually tone free analog to digital converter for audio applications. This digital implementation can be configured for any size DAC in any process with similarly perfect linearity results. These results are published in two papers as reported in Section 7
3. We are working on high order sigma-delta ADC design method with noise-transfer-function optimization to ensure stability and performance for extended input amplitude ranges. This eliminates the need for expensive and inefficient analog methods such as overload detection and integrator clamping in high order sigma-delta ADCs.
Main Results: Early results are very promising that resulted in system level design of a 7th order sigma-delta converter that is stable at almost full input swing with more than 6dB SNR improvement over competitive methods. We also defined novel stability measures and optimized for maximum stability while keeping performance at target range. A journal paper related to this work is under preparation
4. We are building on the earlier proposed Cascaded-Modulator Architecture that is used to reduce the out-of-band noise in DACs. This method can be improved by combining segmentation principle to increase DAC resolution and reduce out-of-band-noise further with the same cost or reduce the cost of mismatch shaping for the same noise resulting in better power and area efficiency.
Main Results: This research is still early in the investigation stage. Basic mathematical model predicts significant gains in out of band noise reduction for the same DAC area. Further modeling and simulation is needed