Cel
Formal verification is the study of algorithms and tools for the development of correct hardware and software designs. Two fundamental problems in formal verification are temporal logic model checking -- given a mathematical model of the system and a temporal-logic formula that specifies the desired behavior of the system, decide whether the model satisfies the formula, and synthesis -- given a temporal-logic formula that specifies the desired behavior, generate a system that satisfies the specification with respect to all environments. Formal verification improves earlier verification methods, which are based on simulation and are thus neither exhaustive nor fully automatic.
Formal verification is Boolean: the system may either satisfy its specification or not satisfy it. The objective of this research is to add a quality measure to the satisfiability of specifications of reactive systems, and to use it in order to formally define and reason about quality of systems and in order to significantly improve the quality of automatically synthesized reactive systems. We plan to do so by developing a theory of multi-valued specification formalisms -- temporal logic and automata, studying the algorithmic aspects of the new formalisms, and suggesting novel applications of multi-valued automata in verification, design, and synthesis of reactive systems.
Dziedzina nauki
Zaproszenie do składania wniosków
ERC-2011-StG_20101014
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System finansowania
ERC-SG - ERC Starting GrantInstytucja przyjmująca
91904 Jerusalem
Izrael