Final Report Summary - SPEAR (Specialisable, Programmable, Efficient and Robust Microprocessors) This project explored the design of flexible and energy-efficient processors suitable for a wide-range of compute-intensive tasks. We designed and prototyped an architecture which supports large numbers of simple cores and provides low-level control over how these individual cores communicate and collaborate. The memory system is also highly configurable. The cores, on-chip interconnect and on-chip memories provide a sea of resources, not unlike an FPGA, that can be composed and used in many different ways to optimise the execution of software. Performance and power efficiency gains are possible through specialising the mapping of software to hardware in ways which are not possible/profitable on existing commercial platforms. Our test chip can perform around 60 billion (32-bit) operations per second while consuming ~250mW.
