Final Report Summary - TIPS (Technology development and fabrication of Integrated solid-state Power Switches)
Executive Summary:
The main goal of this project was to develop highly integrated bi-directional power switches, of the kind commonly employed in building matrix converters. The activity encompassed a design phase, followed by actual fabrication and experimental evaluation and validation of the proposed solutions. The power switches for the matrix converter are based on power bond-wire-less double-sided cooled sandwich power module packaging technology. TRL6 technology maturity is demonstrated by developing, delivering and testing optimum interconnect and cooling solutions.
This project generates the knowledge and understanding required to design and manufacture efficient and reliable power modules; it delivers fully qualified modules compliant with the aircraft operational environment. To ensure compliance with the applicable reliability requirements, the design was based on a built-in reliability approach during all stages of the workflow. The outcomes of this project will benefit European competitiveness in the field of power conversion system development for avionic applications and will have significant spin offs to other application domains.
This project addresses and delivers a number of novel technology features: in particular, use of wide band-gap (Silicon carbide, SiC) was a key aspect, in view of the technology challenges it poses. An important aspect of this project is the investigation of the capability offered by silicon-carbide for the modularisation of power conversion equipment, a key aspect of exploitation for increased industrial competitiveness.
It was a 16 month project involving 1 investigator, 2 researchers. The total value is 534k€ and the requested total contribution is 401k€.
Project Context and Objectives:
The overall work plan has been devised to provide a systematic and comprehensive approach to the various components of the project. Coordination and management tasks are undertaken as a single work package which ran through the whole duration of the project. The work plan was structured in 6 distinct work packages organized to generate at the same time a sequential progression and a continuous feedback of knowledge. The structure of the project has been designed to reflect the anticipated tasks required to move from the definition of requirements and preliminary design study to a solid design for manufacturability and reliability. Testing and qualification will be according to aircraft operational requirements.
PRIMES puts a huge effort in developing virtual prototyping solutions for power electronics components and systems, combined to a prototyping and characterization platform to be able to design, simulate, manufacture and characterize new power module technologies.
In a technological point of view, PRIMES has developed several integration technologies, for insulating or conductive materials to electrical system topologies.
PRIMES has demonstrated expertise and manufacturing capability of solid-state power switches for the avionic/aerospace industry. It is independent in manufacturing and/or sourcing the required assembly parts, including interconnects and heat-sink. PRIMES has experience in the application of electrical, thermal and mechanical co-design is essential as is the knowledge and capability of carrying out technology qualification tests in conformity with standard avionic specifications to ensure the achievement of TRL6 level.
In the first Workpackage, concerning the management of the project, the main objective is to ensure successful and timely development of all phases of the project by proper steering and organization and ensuring availability of necessary tools and facilities at all times.
The second WP consisted in designing the elementary switch, by using innovating technologies as power bump technology for example. PRIMES design rules and co-simulation tools helped us to optimize this design.
The third WP is about manufacturing of power switches. It was possible thanks to PRIMES Clean Room, used for micro-assembly process. First of all, we had to set-up the process by adapting typical know-how to these specific integrated objects. Then we manufactured all needed switches for the project.
The fourth WP consisted in designing and co-simulating cooling system, by using chipper and reliable solutions.
The fifth WP was the longest one because we had to manufacture all power matrix converters and characterize the whole packaging technology by using several reliability and ageing test benches.
At last, the sixth Work Package explored a feasibility study in the integration within the power switch of monolithic integrated gate driver chips.
Project Results:
A kick-off meeting has be held soon after the official project start. After that, periodic meetings were planned for all involved personnel to review progress and discuss continuation. Informal meetings and interactions between participants were foreseen on a continuous basis for synergy optimisation and maximization of the potential outcome of the research effort.
In the second Work package, the aim of this work was to design and co-simulate the elementary switch:
This system has to be a highly integrated bi-directional power switch, using 2 MOSFET in Silicon Carbide. Chosen technology for inside interconnections is Bump Technology. The main reasons are the ability to deeply decrease layout and global dimensions, and the use of a double side cooling system.
These studies were possible thanks to 2 softwares: Solid Edge ST and Q3D for RLC model.
Electrical schematic to be respected is two SiC MOSFET connected by each source as a middle point.
The system is composed by two direct bounding copper (DBC), themselves composed by one copper layer, one ceramic layer (aluminum nitride, AlN) and another copper layer.
Between these two DBCs, there are some copper bumps, and some aluminum wire bonding, which permit to link these two DBCs. And there are the two silicon carbide dies which produce the thermal power that must be dissipated.
The design consists in creating the layout of copper layers, optimizing bump placement and minimizing loop inductance.
We use wire bonding technology to connect Signal potentials, e.g. Gate and Source potentials. Two signal terminals will be brazed for the external connection, for each semiconductor die. Exactly the same assembly can be used for the other MOSFET, placed on the top, and connected by brazed copper balls (bump technology).
Connections are made by brazed copper balls, but the placement and dimensions are chosen with a compact aspect and mechanical function compromise.
After this substrate design, we had to create signal and power terminals.
For signal terminals, simple sheet metal parts are created with a hole at one extremity to be able to connect it easily. The curve shape will permit to have a centered connection between the two substrates. And so we will have three of them to connect the two gates and the common source.
Finally, for the power terminals, we chose to use another DBC substrate with each drain potential on each copper side. The objective is to limit loop inductance and so a busbar effect can be used with this two face structure. Two “faston” connectors will be brazed to ensure easy connection.
At least, we obtain a compact elementary cell, with very small dimensions.
Following thermal study, we needed to design some small heat sinks on bottom side of each DBC.
These copper heat sinks will be brazed on DBC by HMP solder process.
For plastic parts, we consider using machining plastic parts instead of molding parts (for higher quantities) or printed parts (leakage with cooling system). So the design takes into account the manufacturability.
We build the packaging around the possibility to put together three systems in series.
First of all, two objects are built, above and below the system and enclose the two dissipators. These objects are linked with glue and screws.
Another part is built, which permits to link several previous assemblies, the sealing is ensured by a joint which is placed in a cavity.
A part which permits to link the pump (to inject the cooling fluid) and the assembly have to be built. This link will be ensured thanks to two parts. The first one is a plastic part with a gas thread which is linked with the pump. And the second one is an object which it permits to link the assembly with the object linked to the pump.
Each part can be assembled to form a Matrix converter with 3 elementary cells.
All power terminals are on the same side for an easy connection. The other side gives us all signal terminals, to an easy connection to the driver.
To conclude this design step, the design of this integrated matrix converter is based on Bump Technology. This technology allows us to highly integrate the electrical function.
We were obliged to use wire bonding for signal terminals (Gate/Source) but very low current is involved for these interconnections.
For plastic packaging parts, an improvement would be using molding plastic instead of tooling plastic. And global dimensions should be optimized to improve compacity.
The aim of the third Work Package is to establish a manufacturing and assembly process for the power switch suitable for TRL6 demonstration and higher.
The objective is to deliver 25 prototypes to the Topic Manager for his electrical system characterizations, minimum 15 fully fonctionnal.
During this project, we have access to a prototype manufacturing platform, including a 250m² ISO5 and ISO7 clean room. Equipment in this clean room is composed by solder reflow furnaces (convection or static furnace under vacuum and specific gazes), some pick&place or dispensing robots, surface treatment by plasma, X-ray and SAM...
All equipment in this clean room allow to prototype typical assembly technologies (wedge bonding, standard solder paste...) and all innovative technologies as bump technology for example.
In this first part, a flowchart process is detailed:
- heat sink report: brazing heat-sink with HMP solder preform, on 3051 SST Furnace [Vacuum, N2, H2]
- Die attach: brazing die with HMP solder preform, 3051 SST Furnace [Vacuum, N2, H2]
- signal wire bonding: connection with 150µm wire bonding, on HB50 TPT Wire bonder
- bump connection: Copper ball and terminals brazed with SAC305 solder paste, on SIKAMA Furnace - hotplates
- Gluing: Gluing the unit matrix converter on plastic part, Manual dispensing, 110°C oven
- Dielectric gel: insertion of dielectric gel by syringe, Manual dispensing
- Assembly: connection with other plastic parts by screwing
Before the effective manufacturing, we had to calibrate each process. The first brazing process (heat-sink and die attach) or not so innovating and so PRIMES process rules are efficient to realize these steps. Wire bonding process is more delicate, due to small dimensions of electrical pads and low space (small loop). The diameter of the aluminum wire is finally 150µm.
The next step consists in Bump process. At the same time, signal terminal and Power substrate terminal will be brazed, with the same SAC305 solder paste. Mechanical tools help us for a good positioning.
First series of prototypes were manufactured for ageing tests (WP4). We kept 25 prototypes for final delivery.
In total, about 60 prototypes have been manufactured.
The forth Work package is about the thermal analysis of the system and the good dimensioning of the electro-thermal-fluidic study.
The physical properties don’t allow these dies to reach a certain temperature (about 150°C). To fulfill this goal, a study of the system had to be done and a cooling system has been built.
These studies are possible thanks to 2 softwares: Flotherm XT and Solid Edge.
So in a first part, a theoretical study has been realized with some calculations of temperature and thermal flow. After, several simulations have been done thanks to the software Flotherm. Then the packaging of the cooling circuit has been built thanks to the software SolidEdge. And finally, simulations with the whole system.
First, a theoretic study was done for first approach. We searched some data about the different materials of the system to do a thermal study of it.
For each components or materials, we note the thermal conductivity, the thickness. And we notice that the DBCs are bigger than the dies, so we suppose that the thermal transfer spread through the DBCs like a cone with an angle of 45°.
We noticed that the system is symetric, the high part and the low part are approximatively the same (without consider the wire bonding and the signal terminals on the right of the system), and the two dies produce the same power. The Power substrate is neglect too. For this symetric reason, only one side of the system will be studied to calculate the die temperature.
Thanks to an Excel table, all the thermal resistances are calculate (for each material of the DBC, the surface of the thermal source is calculated, indeed it’s not the same because of the propagation cone). Then, the convection coefficient is calculated to have all the necessary data in this study. To simplify the first calculation, we use the correlation of thermal convection along a plate. At first, water is used as cooling fluid with a speed of 5 m/s and so we obtain a Reynolds number less than 500000 and so there is a laminar flow. After using several equations for the Nusselt number, then to calculate the Prandtl, and Reynolds numbers, there are all the data to calculate the convection coefficient and so to calculate the convection thermal resistance of the system. With this thermal resistance (convection and conduction) the theoretical die temperature is calculated.
With all these data, the die temperature theoretically obtained is about 255°C, that is too high, and that’s why a taken decision were to use a dissipator on the top DBC copper layer. The size of this dissipator is chosen in function of the thermal source surfaces calculated previously. The chosen size is finally 5X7mm with a bottom of 0.5mm and with 4 fins spaced 1mm, 1mm wide and 2mm high.
With this dissipator, in the same way of calculation, we obtained a die temperature about 160°C.
After this calculation studies, we used simulation Tools for a better optimization.
A dissipator system is at first build with SolidEdge, centered on the die. Thanks to this system, the heat flux will dissipate by conduction through the dissipator and by convection with the cooling fluid which will pass in the dissipator (like described in the previous part).
This new assembly is imported on Flotherm XT. On this software a cooling circuit is built around this assembly .
After these building steps, first simulations are realized with these different data:
-The cooling fluid used is glycol water (40%), this fluid has been proposed by the topic manager after the theoretical study.
-The dimension of the dissipator is 5x7 mm.
-The ambient temperature is 35°C.
With this data, some other data vary to study the evolution of the die temperature. Some results are obtained with the variation of the water glycol velocity (at the input section) and temperature, and the dissipator fin length
The selected data are:
-The fin length is 2 mm because after this value, the diminution of temperature is not enough substantial.
-For the same reason, the glycol water volume flow is 15.10-5 m3/s at the input.
-About the glycol water temperature, the worst value is used to realize simulations, this value is 20°C.
With these data, and thanks to the Flotherm XT software, we obtain a distribution of temperature through the system and especially a die temperature.
There is a good propagation of the heat flux but the temperature is too high (196°C), so a solution to reduce this value have to be found. And this solution is to reduce the die solder thickness and use the most conductive solder (Sn Ag).
In the first part the die solder had a thickness of 100µm and in this part we have reduced it to 50µm. With this die solder thickness there is the same distribution of temperature but these ones are lower. Indeed the die temperature is now about 105°C.
This is very lower than the expected temperature so the volume flow can be reduced, we make another simulation with a volume flow of 5.10-5 m/s and the temperature obtained is about 145 °C.
Now that the correct temperature is reached, the part about the design of the cooling packaging begins (part of Design Work Package).
Once all plastic parts have been designed, we checked the distribution of temperature of the system. The obtained temperatures for each die are approximately the same (between 135°C and 140°C), this is possible because the cooling fluid doesn’t heat a lot along the circuit, indeed its temperature increases by three degrees.
Thanks to this software, the pressure difference between the input and the output can be studied, and in this case this difference isn’t excessive: about 0,14 bar.
This was a very acceptable temperature/pressure values, then the experimental part can start.
The fifth Work Package deals with Electrical Characterization and reliability:
The goal of the first experiment is to evaluate the behavior of the prototype at different values of water flow inside the cooling circuit when the two MOS transistors are working as closed switches. We measure inlet/outlet temperature of the system at different water flows (9 L/min, 7 L/min and 5 L/min). And even with the lowest water flow (5 L/min) water temperature increased only about a couple of degrees, that is very reassuring.
All Unit matrix converters were tested in I(V) Static characterization, thanks to PRIMES Keysight B1505 component analyser.
In reliability point of view, the first test was thermal shocks. The experiment consists in subjecting components to a temperature cycling from – 60°C to 150°C, specified in the DO 160 standards.
In fact, TIPS unit matrix converters are inserted inside a chamber of CTV 2 120 oven, from BIA supplier, which contains two chambers : the lower one is a cold chamber set to -60°C and the upper one is a hot chamber set to 150°C.
The devices under test move from one chamber to another thanks to an elevator during a short period (maximum 7 seconds) so it produces a thermal shock.
Then the operation is repeated fifty times, following cycles with a period of one hour containing 30 minutes at cold temperature and 30 minutes at hot temperature.
The study lead to the validation of the power switches (5 under test) in the severe conditions of stress test.
The products undergo the test with fifty thermal shocks without being damaged: brazing interfaces remain intact.
The second ageing test was typical thermal cycling test:
The experiment consists in subjecting the components to variations (not shocks) of temperature specified in the DO 160 standard for at least 500 cycles.
In fact, the prototypes are inserted inside the temperature test cabinet CTS TS-70/280-20.
The devices under test undergo a variation of temperature between 150°C and -55°C (stable during 5 min) and the transition between the two values takes 25 min (about 8°/min).
The study leads to the validation of the power switches in these severe conditions of stress. The only damage is located in a delamination of the copper metallization of power DBC. It is not a surprise because we know the limit of DBCs during such a test when they are without any connection. We can correct it by using other type of substrate, or specific Power Electronic Busbar...
The other ageing test consists in Power cycling. This test is based on thermomechanical stress on interconnections, by self heating created by high current cycling.
Chosen gradient of temperature is ΔTJ = 80°C. The objective was to have at least 100 000 cycles without big VDS variation (less than 10%). It corresponds with a life time of 20 years for typical Embedded systems.
First, we had to calibrate each prototypes to calculate thermosensitive parameter. Then we adjusted current and cooling system to fix ΔTJ = 80°C, and we monitored power switches to measure VDS.
The result of this test is quite positive because we managed to obtain 133700 cycles before the VDS value raised about 10% from its beginning value. All this campaign was made with pre-prototypes (process not still robust and fixes). So we are very confident for future ageing tests with this structure.
The last Work package explored a feasibility study in the integration within the power switch of monolithically integrated gate driver chips. First, we can easily imagine that such a chip have to be implemented very close to power MOSFETs. 3D structure of bump technology have to be compatible with electrical and mechanical dimensions. That’s why monolithic solution has to be explored.
By looking at existing Integrated Gate Driver (IGD) dies, we can see packaging process is compatible with our TIPS micro-assembly process: die attach at the same time, wire bonding with the same or similar aluminum wire bonding, and soldering of a logical connector instead of specific signal terminal. Dimensions of final prototype will have to be nearly the same...
Potential Impact:
Primes organizes the communication about the TIPS ‘ project as more as possible during all the project cycle:
First main event March 18th & 19th 2015 : at Decielec, an International Congress on Energy Management Systems and Power Electronics based in Tarbes. We held a stand at the exhibition on the B to B area where we exposed a poster about TIPS’ project. This event allows our organization to strengthen many contacts ans also to create new professional relationships. As we are settled in Tarbes and very well known to the organiser of this congress our participation was free of charge.
Furthermore we do communicate continuously throughout the life of the project to our industrial and academic partners, members of Primes Platform. For example the Primes workshop in October 2015 gathering about 50 people (academic researchers and engineers from different industries SME and major industrial groups) a succinct presentation of the project was organized and some participants interested to this project asked for more information. During others events such as the bi-annual Scientific Committee of Primes Platform the project was presented. We do emphasize these events as they gathering main actors of the power electronical community and were free of charge for Primes Association.
At last, just after the dead line of the project, an abstract for a congress has been writen jointly by PRIMES Association and the University of Nottingham (Topic Manager), for the 4th IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA): "Integrated Bi-Directional SiC MOSFET Power Switches for Efficient, Power Dense and Reliable Matrix Converter Assembly".
List of Websites:
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The main goal of this project was to develop highly integrated bi-directional power switches, of the kind commonly employed in building matrix converters. The activity encompassed a design phase, followed by actual fabrication and experimental evaluation and validation of the proposed solutions. The power switches for the matrix converter are based on power bond-wire-less double-sided cooled sandwich power module packaging technology. TRL6 technology maturity is demonstrated by developing, delivering and testing optimum interconnect and cooling solutions.
This project generates the knowledge and understanding required to design and manufacture efficient and reliable power modules; it delivers fully qualified modules compliant with the aircraft operational environment. To ensure compliance with the applicable reliability requirements, the design was based on a built-in reliability approach during all stages of the workflow. The outcomes of this project will benefit European competitiveness in the field of power conversion system development for avionic applications and will have significant spin offs to other application domains.
This project addresses and delivers a number of novel technology features: in particular, use of wide band-gap (Silicon carbide, SiC) was a key aspect, in view of the technology challenges it poses. An important aspect of this project is the investigation of the capability offered by silicon-carbide for the modularisation of power conversion equipment, a key aspect of exploitation for increased industrial competitiveness.
It was a 16 month project involving 1 investigator, 2 researchers. The total value is 534k€ and the requested total contribution is 401k€.
Project Context and Objectives:
The overall work plan has been devised to provide a systematic and comprehensive approach to the various components of the project. Coordination and management tasks are undertaken as a single work package which ran through the whole duration of the project. The work plan was structured in 6 distinct work packages organized to generate at the same time a sequential progression and a continuous feedback of knowledge. The structure of the project has been designed to reflect the anticipated tasks required to move from the definition of requirements and preliminary design study to a solid design for manufacturability and reliability. Testing and qualification will be according to aircraft operational requirements.
PRIMES puts a huge effort in developing virtual prototyping solutions for power electronics components and systems, combined to a prototyping and characterization platform to be able to design, simulate, manufacture and characterize new power module technologies.
In a technological point of view, PRIMES has developed several integration technologies, for insulating or conductive materials to electrical system topologies.
PRIMES has demonstrated expertise and manufacturing capability of solid-state power switches for the avionic/aerospace industry. It is independent in manufacturing and/or sourcing the required assembly parts, including interconnects and heat-sink. PRIMES has experience in the application of electrical, thermal and mechanical co-design is essential as is the knowledge and capability of carrying out technology qualification tests in conformity with standard avionic specifications to ensure the achievement of TRL6 level.
In the first Workpackage, concerning the management of the project, the main objective is to ensure successful and timely development of all phases of the project by proper steering and organization and ensuring availability of necessary tools and facilities at all times.
The second WP consisted in designing the elementary switch, by using innovating technologies as power bump technology for example. PRIMES design rules and co-simulation tools helped us to optimize this design.
The third WP is about manufacturing of power switches. It was possible thanks to PRIMES Clean Room, used for micro-assembly process. First of all, we had to set-up the process by adapting typical know-how to these specific integrated objects. Then we manufactured all needed switches for the project.
The fourth WP consisted in designing and co-simulating cooling system, by using chipper and reliable solutions.
The fifth WP was the longest one because we had to manufacture all power matrix converters and characterize the whole packaging technology by using several reliability and ageing test benches.
At last, the sixth Work Package explored a feasibility study in the integration within the power switch of monolithic integrated gate driver chips.
Project Results:
A kick-off meeting has be held soon after the official project start. After that, periodic meetings were planned for all involved personnel to review progress and discuss continuation. Informal meetings and interactions between participants were foreseen on a continuous basis for synergy optimisation and maximization of the potential outcome of the research effort.
In the second Work package, the aim of this work was to design and co-simulate the elementary switch:
This system has to be a highly integrated bi-directional power switch, using 2 MOSFET in Silicon Carbide. Chosen technology for inside interconnections is Bump Technology. The main reasons are the ability to deeply decrease layout and global dimensions, and the use of a double side cooling system.
These studies were possible thanks to 2 softwares: Solid Edge ST and Q3D for RLC model.
Electrical schematic to be respected is two SiC MOSFET connected by each source as a middle point.
The system is composed by two direct bounding copper (DBC), themselves composed by one copper layer, one ceramic layer (aluminum nitride, AlN) and another copper layer.
Between these two DBCs, there are some copper bumps, and some aluminum wire bonding, which permit to link these two DBCs. And there are the two silicon carbide dies which produce the thermal power that must be dissipated.
The design consists in creating the layout of copper layers, optimizing bump placement and minimizing loop inductance.
We use wire bonding technology to connect Signal potentials, e.g. Gate and Source potentials. Two signal terminals will be brazed for the external connection, for each semiconductor die. Exactly the same assembly can be used for the other MOSFET, placed on the top, and connected by brazed copper balls (bump technology).
Connections are made by brazed copper balls, but the placement and dimensions are chosen with a compact aspect and mechanical function compromise.
After this substrate design, we had to create signal and power terminals.
For signal terminals, simple sheet metal parts are created with a hole at one extremity to be able to connect it easily. The curve shape will permit to have a centered connection between the two substrates. And so we will have three of them to connect the two gates and the common source.
Finally, for the power terminals, we chose to use another DBC substrate with each drain potential on each copper side. The objective is to limit loop inductance and so a busbar effect can be used with this two face structure. Two “faston” connectors will be brazed to ensure easy connection.
At least, we obtain a compact elementary cell, with very small dimensions.
Following thermal study, we needed to design some small heat sinks on bottom side of each DBC.
These copper heat sinks will be brazed on DBC by HMP solder process.
For plastic parts, we consider using machining plastic parts instead of molding parts (for higher quantities) or printed parts (leakage with cooling system). So the design takes into account the manufacturability.
We build the packaging around the possibility to put together three systems in series.
First of all, two objects are built, above and below the system and enclose the two dissipators. These objects are linked with glue and screws.
Another part is built, which permits to link several previous assemblies, the sealing is ensured by a joint which is placed in a cavity.
A part which permits to link the pump (to inject the cooling fluid) and the assembly have to be built. This link will be ensured thanks to two parts. The first one is a plastic part with a gas thread which is linked with the pump. And the second one is an object which it permits to link the assembly with the object linked to the pump.
Each part can be assembled to form a Matrix converter with 3 elementary cells.
All power terminals are on the same side for an easy connection. The other side gives us all signal terminals, to an easy connection to the driver.
To conclude this design step, the design of this integrated matrix converter is based on Bump Technology. This technology allows us to highly integrate the electrical function.
We were obliged to use wire bonding for signal terminals (Gate/Source) but very low current is involved for these interconnections.
For plastic packaging parts, an improvement would be using molding plastic instead of tooling plastic. And global dimensions should be optimized to improve compacity.
The aim of the third Work Package is to establish a manufacturing and assembly process for the power switch suitable for TRL6 demonstration and higher.
The objective is to deliver 25 prototypes to the Topic Manager for his electrical system characterizations, minimum 15 fully fonctionnal.
During this project, we have access to a prototype manufacturing platform, including a 250m² ISO5 and ISO7 clean room. Equipment in this clean room is composed by solder reflow furnaces (convection or static furnace under vacuum and specific gazes), some pick&place or dispensing robots, surface treatment by plasma, X-ray and SAM...
All equipment in this clean room allow to prototype typical assembly technologies (wedge bonding, standard solder paste...) and all innovative technologies as bump technology for example.
In this first part, a flowchart process is detailed:
- heat sink report: brazing heat-sink with HMP solder preform, on 3051 SST Furnace [Vacuum, N2, H2]
- Die attach: brazing die with HMP solder preform, 3051 SST Furnace [Vacuum, N2, H2]
- signal wire bonding: connection with 150µm wire bonding, on HB50 TPT Wire bonder
- bump connection: Copper ball and terminals brazed with SAC305 solder paste, on SIKAMA Furnace - hotplates
- Gluing: Gluing the unit matrix converter on plastic part, Manual dispensing, 110°C oven
- Dielectric gel: insertion of dielectric gel by syringe, Manual dispensing
- Assembly: connection with other plastic parts by screwing
Before the effective manufacturing, we had to calibrate each process. The first brazing process (heat-sink and die attach) or not so innovating and so PRIMES process rules are efficient to realize these steps. Wire bonding process is more delicate, due to small dimensions of electrical pads and low space (small loop). The diameter of the aluminum wire is finally 150µm.
The next step consists in Bump process. At the same time, signal terminal and Power substrate terminal will be brazed, with the same SAC305 solder paste. Mechanical tools help us for a good positioning.
First series of prototypes were manufactured for ageing tests (WP4). We kept 25 prototypes for final delivery.
In total, about 60 prototypes have been manufactured.
The forth Work package is about the thermal analysis of the system and the good dimensioning of the electro-thermal-fluidic study.
The physical properties don’t allow these dies to reach a certain temperature (about 150°C). To fulfill this goal, a study of the system had to be done and a cooling system has been built.
These studies are possible thanks to 2 softwares: Flotherm XT and Solid Edge.
So in a first part, a theoretical study has been realized with some calculations of temperature and thermal flow. After, several simulations have been done thanks to the software Flotherm. Then the packaging of the cooling circuit has been built thanks to the software SolidEdge. And finally, simulations with the whole system.
First, a theoretic study was done for first approach. We searched some data about the different materials of the system to do a thermal study of it.
For each components or materials, we note the thermal conductivity, the thickness. And we notice that the DBCs are bigger than the dies, so we suppose that the thermal transfer spread through the DBCs like a cone with an angle of 45°.
We noticed that the system is symetric, the high part and the low part are approximatively the same (without consider the wire bonding and the signal terminals on the right of the system), and the two dies produce the same power. The Power substrate is neglect too. For this symetric reason, only one side of the system will be studied to calculate the die temperature.
Thanks to an Excel table, all the thermal resistances are calculate (for each material of the DBC, the surface of the thermal source is calculated, indeed it’s not the same because of the propagation cone). Then, the convection coefficient is calculated to have all the necessary data in this study. To simplify the first calculation, we use the correlation of thermal convection along a plate. At first, water is used as cooling fluid with a speed of 5 m/s and so we obtain a Reynolds number less than 500000 and so there is a laminar flow. After using several equations for the Nusselt number, then to calculate the Prandtl, and Reynolds numbers, there are all the data to calculate the convection coefficient and so to calculate the convection thermal resistance of the system. With this thermal resistance (convection and conduction) the theoretical die temperature is calculated.
With all these data, the die temperature theoretically obtained is about 255°C, that is too high, and that’s why a taken decision were to use a dissipator on the top DBC copper layer. The size of this dissipator is chosen in function of the thermal source surfaces calculated previously. The chosen size is finally 5X7mm with a bottom of 0.5mm and with 4 fins spaced 1mm, 1mm wide and 2mm high.
With this dissipator, in the same way of calculation, we obtained a die temperature about 160°C.
After this calculation studies, we used simulation Tools for a better optimization.
A dissipator system is at first build with SolidEdge, centered on the die. Thanks to this system, the heat flux will dissipate by conduction through the dissipator and by convection with the cooling fluid which will pass in the dissipator (like described in the previous part).
This new assembly is imported on Flotherm XT. On this software a cooling circuit is built around this assembly .
After these building steps, first simulations are realized with these different data:
-The cooling fluid used is glycol water (40%), this fluid has been proposed by the topic manager after the theoretical study.
-The dimension of the dissipator is 5x7 mm.
-The ambient temperature is 35°C.
With this data, some other data vary to study the evolution of the die temperature. Some results are obtained with the variation of the water glycol velocity (at the input section) and temperature, and the dissipator fin length
The selected data are:
-The fin length is 2 mm because after this value, the diminution of temperature is not enough substantial.
-For the same reason, the glycol water volume flow is 15.10-5 m3/s at the input.
-About the glycol water temperature, the worst value is used to realize simulations, this value is 20°C.
With these data, and thanks to the Flotherm XT software, we obtain a distribution of temperature through the system and especially a die temperature.
There is a good propagation of the heat flux but the temperature is too high (196°C), so a solution to reduce this value have to be found. And this solution is to reduce the die solder thickness and use the most conductive solder (Sn Ag).
In the first part the die solder had a thickness of 100µm and in this part we have reduced it to 50µm. With this die solder thickness there is the same distribution of temperature but these ones are lower. Indeed the die temperature is now about 105°C.
This is very lower than the expected temperature so the volume flow can be reduced, we make another simulation with a volume flow of 5.10-5 m/s and the temperature obtained is about 145 °C.
Now that the correct temperature is reached, the part about the design of the cooling packaging begins (part of Design Work Package).
Once all plastic parts have been designed, we checked the distribution of temperature of the system. The obtained temperatures for each die are approximately the same (between 135°C and 140°C), this is possible because the cooling fluid doesn’t heat a lot along the circuit, indeed its temperature increases by three degrees.
Thanks to this software, the pressure difference between the input and the output can be studied, and in this case this difference isn’t excessive: about 0,14 bar.
This was a very acceptable temperature/pressure values, then the experimental part can start.
The fifth Work Package deals with Electrical Characterization and reliability:
The goal of the first experiment is to evaluate the behavior of the prototype at different values of water flow inside the cooling circuit when the two MOS transistors are working as closed switches. We measure inlet/outlet temperature of the system at different water flows (9 L/min, 7 L/min and 5 L/min). And even with the lowest water flow (5 L/min) water temperature increased only about a couple of degrees, that is very reassuring.
All Unit matrix converters were tested in I(V) Static characterization, thanks to PRIMES Keysight B1505 component analyser.
In reliability point of view, the first test was thermal shocks. The experiment consists in subjecting components to a temperature cycling from – 60°C to 150°C, specified in the DO 160 standards.
In fact, TIPS unit matrix converters are inserted inside a chamber of CTV 2 120 oven, from BIA supplier, which contains two chambers : the lower one is a cold chamber set to -60°C and the upper one is a hot chamber set to 150°C.
The devices under test move from one chamber to another thanks to an elevator during a short period (maximum 7 seconds) so it produces a thermal shock.
Then the operation is repeated fifty times, following cycles with a period of one hour containing 30 minutes at cold temperature and 30 minutes at hot temperature.
The study lead to the validation of the power switches (5 under test) in the severe conditions of stress test.
The products undergo the test with fifty thermal shocks without being damaged: brazing interfaces remain intact.
The second ageing test was typical thermal cycling test:
The experiment consists in subjecting the components to variations (not shocks) of temperature specified in the DO 160 standard for at least 500 cycles.
In fact, the prototypes are inserted inside the temperature test cabinet CTS TS-70/280-20.
The devices under test undergo a variation of temperature between 150°C and -55°C (stable during 5 min) and the transition between the two values takes 25 min (about 8°/min).
The study leads to the validation of the power switches in these severe conditions of stress. The only damage is located in a delamination of the copper metallization of power DBC. It is not a surprise because we know the limit of DBCs during such a test when they are without any connection. We can correct it by using other type of substrate, or specific Power Electronic Busbar...
The other ageing test consists in Power cycling. This test is based on thermomechanical stress on interconnections, by self heating created by high current cycling.
Chosen gradient of temperature is ΔTJ = 80°C. The objective was to have at least 100 000 cycles without big VDS variation (less than 10%). It corresponds with a life time of 20 years for typical Embedded systems.
First, we had to calibrate each prototypes to calculate thermosensitive parameter. Then we adjusted current and cooling system to fix ΔTJ = 80°C, and we monitored power switches to measure VDS.
The result of this test is quite positive because we managed to obtain 133700 cycles before the VDS value raised about 10% from its beginning value. All this campaign was made with pre-prototypes (process not still robust and fixes). So we are very confident for future ageing tests with this structure.
The last Work package explored a feasibility study in the integration within the power switch of monolithically integrated gate driver chips. First, we can easily imagine that such a chip have to be implemented very close to power MOSFETs. 3D structure of bump technology have to be compatible with electrical and mechanical dimensions. That’s why monolithic solution has to be explored.
By looking at existing Integrated Gate Driver (IGD) dies, we can see packaging process is compatible with our TIPS micro-assembly process: die attach at the same time, wire bonding with the same or similar aluminum wire bonding, and soldering of a logical connector instead of specific signal terminal. Dimensions of final prototype will have to be nearly the same...
Potential Impact:
Primes organizes the communication about the TIPS ‘ project as more as possible during all the project cycle:
First main event March 18th & 19th 2015 : at Decielec, an International Congress on Energy Management Systems and Power Electronics based in Tarbes. We held a stand at the exhibition on the B to B area where we exposed a poster about TIPS’ project. This event allows our organization to strengthen many contacts ans also to create new professional relationships. As we are settled in Tarbes and very well known to the organiser of this congress our participation was free of charge.
Furthermore we do communicate continuously throughout the life of the project to our industrial and academic partners, members of Primes Platform. For example the Primes workshop in October 2015 gathering about 50 people (academic researchers and engineers from different industries SME and major industrial groups) a succinct presentation of the project was organized and some participants interested to this project asked for more information. During others events such as the bi-annual Scientific Committee of Primes Platform the project was presented. We do emphasize these events as they gathering main actors of the power electronical community and were free of charge for Primes Association.
At last, just after the dead line of the project, an abstract for a congress has been writen jointly by PRIMES Association and the University of Nottingham (Topic Manager), for the 4th IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA): "Integrated Bi-Directional SiC MOSFET Power Switches for Efficient, Power Dense and Reliable Matrix Converter Assembly".
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