Demonstration of fast parallel architectures for image processing

Informazioni relative al progetto

ID dell’accordo di sovvenzione: INTAS-93-1050

Progetto chiuso

Data di avvio 1 Luglio 1995

Data di completamento 30 Giugno 1996

Finanziato da

• International Association for the promotion of cooperation with scientists from the independent states of the former Soviet Union (INTAS), 1993-

Costo totale € 0,00

Contributo UE € 40 000,00

Coordinato da

Universität Mannheim
Germany

Exploitable results

Demonstration of fast parallel architectures for image processing

The combined working effort concerned the design and the evaluation of parallel and pipelined computer architectures of high data throughput, used for feature extraction from images. It was intended to show their functioning in applications arising in the context of processing particle detector data that need image processing algorithms to run at very high repetition rates. Models have been developed, which physics parameters had to be extracted from detector images. These algorithms were installed and run on simulated data. Many image processing algorithms have been investigated to test the efficiency of this filter process, and commercial computers of different architecture have been benchmarked. The algorithms were analyzed for the possibility of hardware implementation. An algorithm based on multiple local convolutions was chosen as pilot project; it was translated into VHDL, on a behavioural level. The pilot algorithm has been partly installed on a commercial FPGA board which emulated the final destination, the Enable++ processor. Enable++ has been developed which is able to process images in a data driven mode. The processor consists of an extremely powerful FPGA core (for image processing tasks, it is comparable to several thousands of RISC processors), a flexible I/O system, and an active high-speed interconnection network. The main results of the project are: -The identification of a parallel processor architecture which is able to execute image processing algorithms, as they are required high energy physics experiments, at a rate of 100 kHz. -The development of a fully functional prototype of such a processor. It is based on field programmable gate arrays so that it can be reconfigured by software for other, e.g., industrial applications. A large system (Enable++) as well as small system (microEnable) will be offered commercially by a spin-off company (Silicon Software KG).