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Content archived on 2024-06-18

European Library-based flow of Embedded Silicon and test Instruments

Objective

This project aims to increase European Integrated Circuits (IC) quality and competitiveness by developing generic test instruments and interfaces which will drasticly improve the testability and reliability of ICs.

Presently, production testing of ICs is done by large and expensive Automated Test Equipment (ATE). A disadvantage of this approach is that while the production cost of a transistor decreases with each new technology node, the cost to test these transistors remains flat or increases, especially for ICs with analogue, RF or sensors components. If test was built-in the chip and therefore part of the silicon it would ensure that the benefits of silicon scaling to new technology nodes translate to benefits in test cost. The concept of Built-In Self Test (BIST) is a well-known test solution for digital logic and memories but it is still in its infancy for analogue, RF and sensors. Although solutions do exist for these analogue, RF and sensor blocks they are typically point solutions and only applicable to that specific block. While it does reduce recurring test cost it will increase design and test development costs. Moreover it increases the time to market and risks since a new test solution has to be made

Fields of science (EuroSciVoc)

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Programme(s)

Multi-annual funding programmes that define the EU’s priorities for research and innovation.

Topic(s)

Calls for proposals are divided into topics. A topic defines a specific subject or area for which applicants can submit proposals. The description of a topic comprises its specific scope and the expected impact of the funded project.

Call for proposal

Procedure for inviting applicants to submit project proposals, with the aim of receiving EU funding.

ENIAC-2011-1
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Funding Scheme

Funding scheme (or “Type of Action”) inside a programme with common features. It specifies: the scope of what is funded; the reimbursement rate; specific evaluation criteria to qualify for funding; and the use of simplified forms of costs like lump sums.

JTI-CP-ENIAC - Joint Technology Initiatives - Collaborative Project (ENIAC)

Coordinator

NXP SEMICONDUCTORS NETHERLANDS BV
EU contribution
€ 913 824,00
Address
HIGH TECH CAMPUS 60
5656AG Eindhoven
Netherlands

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Region
Zuid-Nederland Noord-Brabant Zuidoost-Noord-Brabant
Activity type
Private for-profit entities (excluding Higher or Secondary Education Establishments)
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Total cost

The total costs incurred by this organisation to participate in the project, including direct and indirect costs. This amount is a subset of the overall project budget.

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Participants (15)

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