Objectif The novel time-triggered architecture (TTA) is gaining growing acceptance in industry as a generic architecture for highly dependable hard real-time systems. It is therefore important for industry and society in general that the design decisions that are at the core of this architecture are validated by all possible means. It is the objective of the project to validate experimentally the system concepts of the TTA, taking a prototype TTP/C controller chip, developed within the ESPRIT project TTA, as the basis. The experiments determine the error-detection coverage of the TTA in a realistic application by using different hardware and software based fault-injection methods.Work description:FIT uses all applicable hardware and software based fault-injection methods to locate weaknesses in TTA and to search for and evaluate design alternatives to correct these weaknesses. VHDL and C-Sim simulation models, pin level, heavy-ion and software implemented fault-injection techniques will be applied.It is planned that the two-year project will be partitioned into four phases of six months each.In phase I the hypotheses to be tested will be defined. Fault-injection experiments for the different injection methods will be specified. The hardware/software set-up of the experiments will be described.In phase II hardware and software for the individual experiments will be set-up for a typical hard-real-time application, consisting of a TTA cluster with a node-under-test and a golden node.In phase III a first set of fault-injection experiments will be carried out. At the end of phase III results from the different injection experiments will be analysed individually and jointly to merge and globally interpret the results of all experiments. Based on this analysis the experiments for phase IV will be defined.In phase IV a second round of injection experiments will be carried out. At the end of this phase results will be analysed and interpreted and possible improvements in the fault-tolerance mechanisms of the TTA will be considered. Champ scientifique natural sciencescomputer and information sciencessoftware Programme(s) FP5-IST - Programme for research, technological development and demonstration on a "User-friendly information society, 1998-2002" Thème(s) 1.1.2.-5.1.2 - CPA2: Dependability in services and technologies Appel à propositions Data not available Régime de financement CSC - Cost-sharing contracts Coordinateur TECHNIKUM KAERNTEN - VEREIN ZUR ERRICHTUNG DER FACHHOCHSCHULE KAERNTEN Contribution de l’UE Aucune donnée Adresse VILLACHERSTRASSE 1 9800 SPITTAL AN DER DRAU Autriche Voir sur la carte Coût total Aucune donnée Participants (7) Trier par ordre alphabétique Trier par contribution de l’UE Tout développer Tout réduire AB VOLVO Suède Contribution de l’UE Aucune donnée Adresse 405 08 GOETEBORG Voir sur la carte Coût total Aucune donnée CHALMERS TEKNISKA HOEGSKOLA AKTIEBOLAG Suède Contribution de l’UE Aucune donnée Adresse 412 96 GOETEBORG Voir sur la carte Coût total Aucune donnée CZECH TECHNICAL UNIVERSITY IN PRAGUE Tchéquie Contribution de l’UE Aucune donnée Adresse ZIKOVA 4 166 36 PRAHA 6 Voir sur la carte Coût total Aucune donnée MOTOROLA GMBH Allemagne Contribution de l’UE Aucune donnée Adresse HEINRICH-HERTZ-STRASSE 1 65232 TAUNUSSTEIN Voir sur la carte Coût total Aucune donnée TECHNISCHE UNIVERSITAET WIEN - INSTITUT FUER TECHNISCHE INFORMATIK Autriche Contribution de l’UE Aucune donnée Adresse TREITLSTRASSE 3/3/182 1040 WIEN Voir sur la carte Coût total Aucune donnée TTTECH COMPUTERTECHNIK AG Autriche Contribution de l’UE Aucune donnée Adresse SCHOENBRUNNERSTRASSE 7 1040 WIEN Voir sur la carte Coût total Aucune donnée UNIVERSIDAD POLITECNICA DE VALENCIA Espagne Contribution de l’UE Aucune donnée Adresse CAMINO DE VERA S/N 46022 VALENCIA Voir sur la carte Coût total Aucune donnée