Project description
Next-Generation Nanoelectronics Components and Electronics Integration
GOSSAMER successfully developed a fully integrated Flash NAND technology based on the TANOS concept, investigating a large number of architecture and material options.
The project aimed at the development of the technology for very high density Non Volatile Memories for mass storage applications down to the 2X nm technology node. The field is receiving increasing attention, due to the explosion of portable multimedia applications, and is forecasted to exceed 40 Billion US$ total available market by 2010. The dominant technology for this application is the floating gate NAND memory. However severe technological roadblocks (reduction in storage charge and electrostatic interference among neighboring cells) are limiting further scaling beyond the 32 nm node. Charge trapping in dielectric layers seems to be a viable alternative to floating gate. The main challenge is the integration of the different new materials, like tunnel dielectric, trapping layer, top dielectric, metal gate at the target technology node and the achievement of an acceptable trade-off between functionality and reliability (e.g. charge retention and endurance). The project covered material development, cell architecture, modeling of material properties, trapping and conduction behavior in the dielectrics, metal gate materials. Initial studies were performed on available technology 65-45nm (more relaxed for Universities and research centers) to arrive to full process integration and realization of full arrays in a technology in the 28-36 nm range (the best achievable with available lithography) by two major European semiconductor manufacturers. It included memory characterization and reliability testing, with the additional aim of defining standards and procedures for reliability assessment. Technology options for higher integration densities, for a given lithography node, were investigated with the help of public research partners. Following the faster than expected evolution of the floating gate NAND Flash technology, it was decided to anticipate a demonstration of the feasibility of the technology on a large scale device in 45nm technology, and to focus the final demonstration on the proof of the scalability of the TANOS technology towards the 20nm generation.
The project aims at the development of the technology for very high density Non Volatile Memories for mass storage applications down to the 2X nm technology node. The field is receiving increasing attention, due to the explosion of portable multimedia applications, and is forecasted to exceed 40 Billion US$ total available market by 2010. The dominant technology for this application is the floating gate NAND memory. However severe technological roadblocks (reduction in storage charge and electrostatic interference among neighboring cells) are limiting further scaling beyond the 32 nm node. Charge trapping in dielectric layers seems to be a viable alternative to floating gate. The main challenge is the integration of the different new materials, like tunnel dielectric, trapping layer, top dielectric, metal gate at the target technology node and the achievement of an acceptable trade-off between functionality and reliability (e.g. charge retention and endurance). The project will cover material development, cell architecture, modeling of material properties, trapping and conduction behavior in the dielectrics, metal gate materials. Initial studies could be performed on available technology 65-45nm (more relaxed for Universities and research centers) to arrive to full process integration and realization of full arrays in a technology in the 28-36 nm range (the best achievable with available lithography) by two major European semiconductor manufacturers. It will include memory characterization and reliability testing, with the additional aim of defining standards and procedures for reliability assessment. Technology options for higher integration densities, for a given lithography node, will be investigated with the help of public research partners. The final demonstrator will be a fully working memory array in the multi-gigabit range.
Fields of science (EuroSciVoc)
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques. See: The European Science Vocabulary.
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques. See: The European Science Vocabulary.
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FP7-ICT-2007-1
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Funding scheme (or “Type of Action”) inside a programme with common features. It specifies: the scope of what is funded; the reimbursement rate; specific evaluation criteria to qualify for funding; and the use of simplified forms of costs like lump sums.
Coordinator
20864 AGRATE BRIANZA
Italy
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Participants (20)
3001 HEVERLEE
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3001 Leuven
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80686 MUNCHEN
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01099 DRESDEN
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01187 DRESDEN
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38106 BRAUNSCHWEIG
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09599 FREIBERG
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00560 Helsinki
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92300 Levallois-Perret
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T12 YN60 Cork
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2306990 Migdal Haemek
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00185 Roma
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44124 Ferrara
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40125 BOLOGNA
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1322 AP ALMERE
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1322 AP ALMERE
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41121 MODENA
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20133 Milano
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33100 Udine
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44121 Ferrara
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