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Gigascale Oriented Solid State flAsh Memory for EuRope

Project description


Next-Generation Nanoelectronics Components and Electronics Integration
GOSSAMER successfully developed a fully integrated Flash NAND technology based on the TANOS concept, investigating a large number of architecture and material options.
The project aimed at the development of the technology for very high density Non Volatile Memories for mass storage applications down to the 2X nm technology node. The field is receiving increasing attention, due to the explosion of portable multimedia applications, and is forecasted to exceed 40 Billion US$ total available market by 2010. The dominant technology for this application is the floating gate NAND memory. However severe technological roadblocks (reduction in storage charge and electrostatic interference among neighboring cells) are limiting further scaling beyond the 32 nm node. Charge trapping in dielectric layers seems to be a viable alternative to floating gate. The main challenge is the integration of the different new materials, like tunnel dielectric, trapping layer, top dielectric, metal gate at the target technology node and the achievement of an acceptable trade-off between functionality and reliability (e.g. charge retention and endurance). The project covered material development, cell architecture, modeling of material properties, trapping and conduction behavior in the dielectrics, metal gate materials. Initial studies were performed on available technology 65-45nm (more relaxed for Universities and research centers) to arrive to full process integration and realization of full arrays in a technology in the 28-36 nm range (the best achievable with available lithography) by two major European semiconductor manufacturers. It included memory characterization and reliability testing, with the additional aim of defining standards and procedures for reliability assessment. Technology options for higher integration densities, for a given lithography node, were investigated with the help of public research partners. Following the faster than expected evolution of the floating gate NAND Flash technology, it was decided to anticipate a demonstration of the feasibility of the technology on a large scale device in 45nm technology, and to focus the final demonstration on the proof of the scalability of the TANOS technology towards the 20nm generation.

The project aims at the development of the technology for very high density Non Volatile Memories for mass storage applications down to the 2X nm technology node. The field is receiving increasing attention, due to the explosion of portable multimedia applications, and is forecasted to exceed 40 Billion US$ total available market by 2010. The dominant technology for this application is the floating gate NAND memory. However severe technological roadblocks (reduction in storage charge and electrostatic interference among neighboring cells) are limiting further scaling beyond the 32 nm node. Charge trapping in dielectric layers seems to be a viable alternative to floating gate. The main challenge is the integration of the different new materials, like tunnel dielectric, trapping layer, top dielectric, metal gate at the target technology node and the achievement of an acceptable trade-off between functionality and reliability (e.g. charge retention and endurance). The project will cover material development, cell architecture, modeling of material properties, trapping and conduction behavior in the dielectrics, metal gate materials. Initial studies could be performed on available technology 65-45nm (more relaxed for Universities and research centers) to arrive to full process integration and realization of full arrays in a technology in the 28-36 nm range (the best achievable with available lithography) by two major European semiconductor manufacturers. It will include memory characterization and reliability testing, with the additional aim of defining standards and procedures for reliability assessment. Technology options for higher integration densities, for a given lithography node, will be investigated with the help of public research partners. The final demonstrator will be a fully working memory array in the multi-gigabit range.

Fields of science

Programme(s)

Topic(s)

Call for proposal

FP7-ICT-2007-1
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Funding Scheme

CP - Collaborative project (generic)

Coordinator

Numonyx Italy Srl
EU contribution
€ 2 809 402,00
Address
VIA CAMILLO OLIVETTI 2
20864 AGRATE BRIANZA
Italy

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Activity type
Private for-profit entities (excluding Higher or Secondary Education Establishments)
Administrative Contact
Manuela Seminara (Dr.)
Links
Total cost
No data

Participants (20)

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Last update: 19 April 2017

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Permalink: https://cordis.europa.eu/project/id/214431

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