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SiGe hetero MOS- and MOSFET's for ultimate scaling towards sub 100 nanometer


Strained SiGe (or strained Si on relaxed SiGe) in the channel of MOS transistors offers strongly enhanced carrier mobilities and therefore improved switching speeds. SIGMUND will optimise sub 100 nm SiGe pMOS transistors integrated into a full CMOS technology, and will build nMODFET transistors on relaxed buffer layers for NMOS technology.

Lower cost, higher packing density and increased frequency and noise performance are the driving forces behind microelectronics. The development of Si based hetero-FETs is strongly driven by their potential of enhanced mobility and current drive. It is the objective of this project to develop sub 100 nm hetero-FETs of both p and n type based on respectively strained SiGe and strained Si epitaxial layers with characteristics superior to classical FETs and low enough process complexity for industrial acceptance. The p hetero-FET will be developed inside a CMOS technology using selective epitaxial growth in the pMOS active areas only, so avoiding degradation of the nMOS transistors and allowing a higher packing density of logic CMOS. The n hetero-FET requires thin, strain relaxed buffer layers, which will also be developed within the project. The improved performance will extend the Si based technology into the microwave regime.

Work description:
In the first work package the layers required for the pFET and nFET will be grown by CVD epitaxy (both blanket and SEG) and MBE respectively. A substantial part of the work is devoted to the development of sub 100 nm thin strain relaxed buffer layers as virtual substrates. It is also necessary to investigate the influence of layer strain, quantum size effects and device dimensions on carrier transport and device performance. Extensive physical simulations will interact with the experimental work to define the optimal layer configurations for enhanced mobility and current drive. In the second work package specific process modules (low temperature dielectrics and gate formation) with low temperature budget will be developed to avoid strain relaxation and dopant diffusion. Also the problem associated with the presence of SiGe (oxidation, silicidation, junction quality) will be studied. Three pFET runs will be performed: 2 pFET only and 1 full CMOS run with a p hetero- FET and normal nMOS, all making use ofShallow Trench Isolation. With respect to the nFET 2 generations of nFET will be developed with frequencies around 120 GHz and up to 200 GHz, respectively. The third work package will concentrate on Monte Carlo and hydrodynamic simulations to support device design and analyse of the experimental data. The results of device characterisation in a temperature range between 50 and 300K will be fed back into electrical models for device optimisation and for use in predictive circuit simulations for prospective applications. Extensive characterisation will be performed with emphasis on HF measurements. In the fourth work package, an oscillator circuit and a broadband amplifier circuit are planned as IC demonstrators. The potential for a PA and space applications cryo temperatures) will be investigated. The potential of the combination of p hetero-FET and standard nFET respectively n hetero-FET in CMOS ICs will also be assessed.

- Virtual substrates with 50% Ge thin SRB - First pFET in CMOS with simple SQW and mobility of 250 cm?/V.s.
- Second pFET with advanced layer design and mobility of 400 cm/V.s.
- CMOS process with sub 100 nm hetero pFET and home nFET.
- First nFET with 120 GHz operation
- Second 200 GHz nFET using improved sub 100 nm gate technology
- Oscillator (VCO) with operating frequency in the 40 GHz range
- Broadband amplifiers (AMP) with frequencies up to 20 GHz.

Call for proposal

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Kapeldreef 75
3001 Leuven

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Participants (4)

3, Rue Michel-ange
75794 Paris Cedex 16

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Epplestrasse 225
70567 Stuttgart

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Keplerstrasse 7
70174 Stuttgart

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15, Rue Georges Clemenceau
91405 Orsay Cedex

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